The purpose of this work is to study the influence of different parameters on short-circuit type III (SC-III) robustness limit of the IGBT and freewheeling diodes (FWD) beyond the specified datasheet values. SC-III measurements without gate-emitter voltage (VGE) clamping show a reduced SC-III safe operating area (SOA) at higher DC-link voltages because of high collector current peaks (IC,peak) induced by transient gate-emitter overvoltage and subsequent high negative diC/dt values. By applying a VGE clamping circuit, SC-III last-pass collector-current (IC,sat,Lastpass) can be fully recovered to the level of SC-I, even though the IGBT and diode encounter harder conditions in the SC-III event. Parameters such as parasitic inductance (Lpar), load current (Iload) and temperature (Tstart) have an influence on the SC-III robustness limit of the IGBTs and FWDs. Also, the second reverse-recovery peak of the FWD during an SC-III event is strongly influenced by whether the gate-emitter voltage is applied across the sense or load-emitter terminal.

Short-circuit behavior and capability are investigated and optimized during IGBT development. Thereby, knowledge about destruction and high-frequency short-circuit oscillation mechanisms is needed. For the thermal destruction mechanism, filaments are formed shortly before destruction during the thermal runaway itself, whereas for the electrical destruction mechanism strong current filaments are formed by an electrical mechanism, before the self-heating in the filaments leads to a thermal runaway. At low collector-emitter voltages, weak non-destructive filaments exist for a large current range. For both the filament formation and short-circuit oscillations (SCOs), an electric-field peak in the field-stop layer and a quasi-plasma layer beneath the MOS cells are mandatory. For SCOs, which are caused by a periodic storage and release of charge carriers inside the device, additionally, a weak electrical field at the beginning of the drift zone is necessary. Weak, non-destructive filaments and SCOs are likely to occur simultaneously. An increase of the bipolar current gain reduces the operating area with SCOs and increases the electrical short-circuit capability. A simultaneous reduction of the thermal short-circuit robustness can be avoided by advanced p-emitter concepts or (over-)compensated by an improved thermal setup.

Inverters based on power switches, such as IGBTs, in either resonant or hard-switching topologies can, during or after a load-fault, exhibit a transient overvoltage at the collector-emitter leads. In such an event, the maximum allowed collectoremitter voltage may be exceeded and the power switch destroyed. To avoid this, some form of active clamping may be used. In this work, we present a concept of a single possibly co-packed, high-voltage TVS-diode with typical breakdown voltages ranging from 1.2 to 1.7 kV.

This work shows an investigation of repetitive Short-Circuit (SC) operation of 1200 V-15 A IGBT far above the Short-Circuit Safe Operating Area (SC-SOA). The goal behind this work was to perform repetitive SC tests with test conditions provoking the formation of current filaments in the short-circuit pulse, which leads to a nonhomogeneous heating but not to a destruction. The target was to investigate unknown physical effects that lead to device degradation during the repetitive SC test. The IGBT device shows strong deterioration in its blocking characteristic after it was subjected to several 1000 SC pulses at extremely high SC levels.

The continued shrinking of IGBT chips calls for new design approaches to ensure reliable and stable switching operation during the chip lifetime. We demonstrate a new asymmetric gate oxide concept with a designed variable thickness that leads to stable long-term operation in trench IGBTs and reduces the switching delay and the gate charge without sacrificing electrical performance. These claims are supported by longer-term repetitive switching experiments as well as TCAD simulations on a calibrated model.

This work investigates the relation of the two destruction modes, the so-called energy destruction and the electrical destruction, during short-circuit operation of an Insulated Gate Bipolar Transistor (IGBT). The critical energy as a function of the short circuit current reveals a kink indicating the transition between two different failure modes. The failure signatures show that energy destruction takes place at lower currents and electrical destruction at higher currents. This supports the hypothesis that there is a huge current range with non-destructive filaments at low dc-link voltages. For both destruction mechanisms, the final failure occurs locally. For the energy destruction, the current crowding happens very late during the runaway itself, whereas in the case of an electrical destruction, filaments are formed mainly by an electrical mechanism leading to a stronger local self-heating. Both mechanisms take place far above the safe operating area of the chip.

The doping profile of the field-stop zone influences the static characteristics (V ce, sat , V br ) and the dynamic switching characteristics (di c /dt, dV CE /dt, softness) of IGBTs. Furthermore, the short-circuit ruggedness is strongly influenced by the rear side structure of the IGET. In this work, box-like field-stop profiles in combination with a constant p-emitter were analyzed by TCAD simulations. The findings were used to optimize and realize field-stop profiles by proton implantation with the focus to achieve an improved short-circuit ruggedness at the same softness.

Gemas einem Verfahren zum Herstellen von CZ-Siliziumwafern wird ein CZ-Silizium-Ingot oder ein CZ-Silizium-Ingotabschnitt in CZ-Siliziumwafer geschnitten (S100). Ein Parameter von zumindest zwei der CZ-Siliziumwafer wird gemessen (S110). Eine Gruppe der CZ-Siliziumwafer, die innerhalb einer Toleranz einer Zielspezifikation liegen, wird bestimmt (S120). Die Gruppe der CZ-Siliziumwafer wird unter Berucksichtigung des gemessenen Parameters in Untergruppen unterteilt. Ein Durchschnittswert des Parameters der CZ-Siliziumwafer jeder Untergruppe unterscheidet sich unter den Untergruppen, und eine Toleranz des Parameters der CZ-Siliziumwafer jeder Untergruppe ist geringer als eine Toleranz des Parameters der Zielspezifikation. Eine Kennzeichnung, die dafur eingerichtet ist, zwischen den CZ-Siliziumwafern verschiedener Untergruppen zu unterscheiden, wird prapariert (S130). Die CZ-Siliziumwafer, die innerhalb der Toleranz der Zielspezifikation liegen, werden verpackt (S140).

Hydrogen-related donors can be formed by using only a moderate thermal budget, so that this process can be used to create field-stop layers in thin power devices. The electrical characteristics of 1200 V IGBTs and diodes provided with such field-stop layers are presented and compared with the characteristics of conventionally processed devices. Moreover, tailoring the field-stop distribution by multi-energy proton implantations offers new opportunities for optimizing the performance of power devices.

The introduction of thick copper metallization and topside interconnects as well as a superior die attach technology is improving the performance and reliability of IGBT power transistor technologies significantly. The much higher specific heat capacity and higher thermal conductivity increases the short circuit capability of IGBTs, which is especially important for inverters for drives applications. This opens the potential to further optimize the electrical performance of IGBTs for higher energy efficiency. The change in metallization requires the introduction of a reliable barrier against copper diffusion and copper silicide formation. This requires the development of an efficient test method and reliability assessment according to a robustness validation approach. In addition, the new metallization enables interconnects with copper bond wires, which yield, together with an improved die attach technology, a major improvement in the power cycling capability. (C) 2016 Elsevier Ltd. All rights reserved.

A novel power Cu front side chip metallization for insulated-gate bipolar transistors (IGBTs) and freewheeling diodes (FWDs) enabling thick Cu wire wedge bonding on active area is reported. In the continuing race to higher power density, main limitations of IGBT power modules are given by short circuit robustness requirements of the IGBT and power cycling capability of the front side Al wedge bond interconnect. Both topics are addressed by Infineon's 5th Generation of IGBT with XT joining technology [1, 2] enabling power density steps far beyond 30%. The developed Cu metallization with a special barrier layer structure allows Cu wedge bonding with high yield and extremely high reliability. The paper is describing firstly the device fabrication and secondly a novel reliability testing method (based on wafer level) covering the possible impact of the wire bond process.

A method for determining the carbon content in a silicon sample may comprise: generating electrically active polyatomic complexes within the silicon sample. Each polyatomic complex may comprise at least one carbon atom. The method may further comprise: determining a quantity, which is indicative of the content of the polyatomic complexes generated in the silicon sample, and determining the carbon content in the silicon sample from the determined quantity.

In this study we examine proton implanted and subsequently annealed commercially available CZ wafers with the DLTS method. Depth-resolved spreading resistance measurements are shown, indicating an additional peak in the induced doping profile, not seen in the impurity-lean FZ reference samples. The additional peak lies about 10–15μm deeper than the main peak near the projected range of the protons. A DLTS characterization in the depth of the additional peak indicates that it is most likely not caused by classical hydrogen-related donors known also from FZ silicon but by an additional donor complex whose formation is assisted by the presence of silicon self-interstitials.

The demand on silicon based sensors continuously increased since they have been used the first time in particle physics for tracking purposes. In accordance with this development the Institute of High Energy Physics of the Austrian Academy of Sciences (HEPHY) and the European semiconductor manufacturer Infineon Technologies Austria AG engaged in a cooperation to develop prototype p-on-n silicon strip sensors. The sensors of two independent batches with slightly varying production processes are evaluated. To investigate their performance, modules have been assembled with an analogue readout chip (APV25) and operated in an electron beam test. An already well-studied problem of poorly isolated strips, restricted to a small region of the sensor could be further investigated at one sensor and has proven to be cured at the others. Therefore charge sharing effects and their dependency on the bias voltage have been investigated on different regions of the sensors. Furthermore the recorded data of the modules, including one gamma irradiated, document the functionality of the devices.

A failure mechanism in the edge termination of a 1200V IGBT during overcurrent turn-off is studied with simulations and verified by experiments. The position of the destruction in the experiment can be correlated to the formation of a critical filament in the simulation. The destruction mechanism is investigated in detail. It is only observed if the IGBT enters its current saturation regime. I.e., the IGBT survives a turn-off from the same current level for an increased gate voltage. It is shown that an IGBT provided with a properly-designed High Dynamic Ruggedness (HDR) edge termination structure [1] is no longer susceptible to the destruction mechanism.

Deep‐level defects remaining in the upper half of the band‐gap of silicon implanted with protons at fluences and annealing temperatures typically used for proton‐implantation doping are investigated. For proton fluences in the range of several 1013 cm−2 to several 1014 cm−2, a multitude of deep‐level defects remain active in comparatively high concentrations of up to 1013 cm−3 even after anneals at temperatures up to 500 °C. The detected deep‐levels are assigned to known lattice defects on the basis of their electrical characteristics obtained by Fourier‐transform DLTS measurements. Despite the low oxygen content of the float‐zone silicon used, a large number of the detected defects are ascribed to (non‐)hydrogenated vacancy‐oxygen defects. The annealing temperature ranges, in which the deep‐level defects were detected, are shown. Furthermore, the dependencies of the deep‐level defects on the proton fluence and their depth distributions in the implantation profile are investigated.

Protons with energies of 1 MeV and 2.5 MeV were implanted into a p-doped silicon wafer and then the wafer was annealed at 350 °C for one hour. This resulted in two n-doped layers in the otherwise p-doped sample. The carrier concentration was measured using spreading resistance profiling while the positions of the four pn-junctions were measured using electron beam induced current measurements. The carrier concentration is not limited by the available hydrogen but by the concentration of suitable radiation induced defects.