An integration scheme for realizing strained n-channel metal-oxide-semiconductor field-effect transistors (nFETS) with embedded silicon-carbon (e-Si: C) source/drain (S/D) stressors formed in close proximity to the channel was demonstrated. The stressors are termed channel-proximate (CP) Si: C S/D stressors, whose proximity to the channel improves their effectiveness in contributing to tensile strain in the channel region. Numerical simulation was performed using the finite-element method to assess the strain enhancement due to CP Si: C S/D. Key process development and material characterization were performed to understand the interaction between dopants and substitutional carbon concentration C-sub. Unstrained control nFETs, nFETs with conventional Si: C S/D formed after spacers, and nFETs with CP Si:C S/D were fabricated. The nFET with CP Si: C S/D stressors achieved a drive current I-on enhancement of similar to 19 and similar to 8% over unstrained nFET and nFET with conventional Si: C S/D, respectively. The impact of channel orientation on I-on enhancement was also investigated. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3493601] All rights reserved.

We report the first integration of a high-compressive-stress diamond-like carbon (DLC) liner stressor with gate-all-around Si nanowire p-channel field-effect transistor (FET). DLC liner stressors with thicknesses of ~ 20 and ~ 40 nm were formed on p-FETs to induce high compressive strain in the channel region. As compared with nanowire p-FETs without liner stressor, substantial enhancements in I ON and saturation transconductance G MSat were observed on p-FETs with DLC liner stressors. A thicker DLC liner stressor leads to a larger performance enhancement.

We report the integration of a novel selenium segregation (SeS) technology in the silicide contact of strained n-MOSFETs featuring silicon-carbon Si 0.99 C 0.01 source/drain (S/D) stressors. SeS at the NiSi:C/n-Si 0.99 C 0.01 interface leads to the achievement of low Schottky barrier height and reduced silicide contact resistance R CSD . At a fixed I OFF of 100 nA/ mum, the improved silicide contact technology employing SeS contributed to a 20% drive current I ON enhancement and 30% total series resistance R Total reduction over control strained devices. The R Total improvement is primarily due to the reduction of external series resistance R EXT , which is due to a reduced R CSD at the NiSi:C/n- Si 0.99 C 0.01 interface. Comparable DIBL, V Tsat and gate leakage density were observed for strained n-MOSFETs with or without the SeS. The impact of introducing Se in the embedded Si 0.99 C 0.01 S/D stressor on tensile stress level in the channel region of strained n-MOSFET was also investigated.

We report the first integration of selenium (Se) segregation contact technology in ultrathin-body (UTB) n-MOSFET featuring Ni fully silicided source and drain. During the Ni silicidation process, the implanted Se segregated at the NiSi-n-Si interface, leading to significant reduction of Schottky barrier height and contact resistance. The UTB n-MOSFETs integrated with Se segregation (SeS) contact technology show significant external series resistance reduction and drive current performance enhancement. Drain-induced barrier lowering and gate leakage current density are not adversely affected by the SeS process.

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si 0.8 Ge 0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si 0.8 Ge 0.2 S/D p-FETs. The I Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.

We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.

We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values reported-to-date, and its device integration for contact resistance reduction in n-FETs. A thin solid Antimony (Sb) layer is inserted beneath Ni prior to S/D silicidation, acting as a large source of n-type dopants. After silicidation, a very high concentration of Sb is incorporated at the NiSi/Si interface. This solid Sb segregation (SSbS) process reduces the effective SB height and parasitic series resistance. The SSbS process leads to enhanced n-FET performance without degradation in off-state leakage.

We report a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height Phi Bn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low Phi Bn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with and without Se segregation. When integrated in nanoscale SOI n-FETs with Ni-silicided Si:C S/D, the new Se-segregation contact technology achieves 36% reduction in total series resistance and 32% I ON enhancement. Linear transconductance G MLin also shows large enhancement in the sample with Se-segregated contacts.

We report for the first time a new process technology for boosting the Ge content in SiGe source/drain (S/D) stressors to increase strain and performance levels in p-FETs. By laser-induced local melting and inter-mixing of an amorphous Ge layer with an underlying Si 0.8 Ge 0.2 S/D region, a graded SiGe S/D stressor is formed upon recrystallization. Peak Ge content in the graded SiGe S/D is doubled over the as-grown film. Raman analysis confirmed the retention of high S/D strain levels due to the rapid non-equilibrium recrystallization process. The new process technology developed here employs several simple additional steps, including amorphous Ge deposition and laser anneal (LA). For a p-FET with Ge enriched S/D, 21% and 12% I Dsat enhancement at a fixed I OFF of 2times10 -8 A/mum is observed over control p-FETs with Si 0.8 Ge 0.2 S/D formed by RTA and LA, respectively.

The electron Schottky barrier height ΦBn modulation for NiSi and PtSi formed on selenium-implanted n-type Si (100) has been experimentally investigated. Selenium (Se) segregation is observed at the silicide/n-Si(100) interface during silicidation process. ΦBn of 83 and 120 meV were achieved for Se segregated NiSi and PtSi on n-Si (100) interfaces, respectively. Contrary to previously reported Fermi level depinning effect in monolayer Se-passivated n-Si (100), the low ΦBn achieved in this work points to metal silicide Fermi level pinning near to conduction band EC of n-Si (100).

We explore a novel silicide contact technology for effective Schottky barrier height Phi(Bn) and contact resistance reduction, which is compatible with an advanced silicon-carbon (Si1-xCx) source/drain (S/D) stressor technology. The new silicide contact technology incorporates selenium (Se) that is coimplanted with S/D dopants into the silicon-carbon S/D prior to nickel silicidation, leading to the segregation of Se at the NiSi:C/n-Si0.99C0.01 interface and the achievement of excellent ohmic contact characteristics. We demonstrate that the Se-coimplantation process contributes to a 23% drive current enhancement in a strained silicon-on-insulator n-MOSFET. The enhancement is attributed to the decrease of external series resistance which is primarily due to the reduction of silicide contact resistance.

We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20% reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement.

We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF -state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V.

We explore a novel integration approach that introduces valence-mending adsorbates such as sulfur (S) or selenium (Se) by ion implantation and prior to nickel silicidation for the effective reduction of contact resistance and Schottky barrier (SB) height at the NiSi/n-Si interface. While a low SB height of ~0.12 eV can be obtained for NiSi formed on S-implanted n-Si, the insertion of a 1000degC anneal prior to silicidation leads to S out-diffusion and loss of SB modulation effects. We demonstrate that Se-implanted Si does not suffer from Se outdiffusion even after a 1000degC anneal, and subsequent Ni silicidation formed an excellent ohmic contact with a low SB height of 0.13 eV. Se segregation at the NiSi/n-Si (100) interface occurred. Implantation of Se and its segregation at the NiSi/n-Si interface is a simple and promising approach for achieving reduced SB height and contact resistance in future high-performance n-channel field-effect transistors.

We report a new method of forming nickel silicide (NiSi) on n-Si with low contact resistance, which achieves a Schottky barrier height of as low as 0.074 eV. Antimony (Sb) and nickel were introduced simultaneously and annealed to form NiSi on n-Si (100). Sb dopant atoms were found to segregate at the NiSi/Si interface. The devices with Sb segregation show complete nickel monosilicide formation on n-Si (100) and a close-to-unity rectification ratio. The rectification ratio Rc is defined to be the ratio of the forward current to the reverse current, where the forward and reverse currents are measured using forward and reverse bias voltages, respectively, having the same magnitude of 0.5 V. This process is also compatible and easily integrated in a CMOS fabrication process flow.

We report on further performance optimization in a novel n-channel transistor (n-FET) with beneath-the-channel strain-transfer structure (STS) and embedded silicon-carbon source/drain (Si:C S/D) stressors. The incorporation of SiGe STS couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. In addition, a two-step recess-etch was used to bring the double-recessed S/D stressors in closer proximity, increasing their lattice interactions with the channel and the STS, thereby significantly increasing the saturation drive current Ionmiddot enhancement over control devices.

We report a new source/drain-extension-last (SDE-last) process flow to incorporate in situ doped and lattice-mismatched source/drain (S/D) stressors extremely close to the channel edge for increased strain and reduced series resistance. This process enables the introduction of S/D stressors with much larger than reported lattice-mismatch at the end of the front-end process, thereby minimizing the thermal budget experienced by highly strained heterostructures which could possibly relax strain. For the first demonstration of this concept, an in situ phosphorus- doped silicon-carbon (SiCP) SDE was employed and integrated in a SOI N-FET. A record-high substitutional carbon concentration of 2.1% was used to realize very significant strain effects.

We report the first demonstration of dopant-segregated metal-semiconductor-metal (DS-MSM) heterostructure on Gate-All-Around Si quantum wire field-effect transistor (QWFET), achieving low external resistance and possibly injection velocity enhancement. ION enhancement of 72% and 26% over conventional QWFETs are obtained for n- and p- DS-MSM QWFETs, respectively. Record high single Si QWFET ION, normalized by quantum wire diameter, of 4.03 mA/mum (n-DS-MSM QWFET) and 1.5 mA/mum (p-DS-MSM QWFET) are reported. In addition, larger ION values are observed for <100> as compared to <110> channel orientation DS-MSM QWFETs.

In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance