This paper reports RF performance of 2.5D Metal-Insulator-Metal CAPacitors (MIMCAPs) within a 300 mm silicon (Si) interposer. The MIMCAPs use both high-k dielectric and 3D oxide-stud patterning to simultaneously achieve high capacitance density, high breakdown voltage and high Self Resonance Frequency (SRF). DC capacitance densities exceed $30 \text{fF} / \mu \mathrm{m}^{2}$ calculated using the parallel plate approximation. Shunt capacitors show SRF between 60-70 GHz (2 pF), 40-50 GHz (4 pF) and 30-40 GHz (9 pF). Series capacitor of 2 pF shows a SRF between 25-30 GHz. Such capacitors can be used for both supply decoupling and as circuit elements for various chiplets mounted on the silicon interposer.

Advanced system integration for mmWave and sub-THz applications demands cost-effective platforms capable of delivering low-loss, high-performance passive components while maintaining scalability for high-volume manufacturing. We have previously demonstrated such a low-loss 300 mm RF silicon interposer platform operating up to 330 GHz, featuring low-resistivity silicon, a novel non-PFAS photo-imageable dielectric (CYCLOTENE® XP80), and copper redistribution layers (RDL) [1]. In this paper, we present scalable equivalent circuit models for passive components, including transmission lines and inductors, tailored to this RF interposer platform. The proposed models accurately predict performance across a wide inductance range, showing excellent agreement with both full-wave electromagnetic simulations and measurements. The modeling approach combines constant reactive elements with frequency-dependent resistance to capture conductor and substrate losses. Model parameters are geometry-and process-dependent, enabling predictive scaling across different designs and technology nodes. The transmission line model is validated up to J-band (220–330 GHz), extending the methodology into the sub-THz regime. The practical impact of the models is demonstrated from a VCO design perspective, where accurate prediction of self-resonant frequency (SRF) and peak quality factor (Q) is essential for optimizing phase noise and tuning range. This work establishes the foundation for a comprehensive RF interposer design library, bridging full-wave electromagnetic analysis and circuit-level implementation to accelerate the development of high-performance mmWave and sub-THz systems.

We utilise laser assisted flip-chip bonding for the hetero-integration of an indium phosphide (InP) power amplifier chiplets onto the imec 300 mm RF silicon interposer with a 40 um pitch. We show how laser assisted bonding (LAB) can be directly responsible for ensuring we can attach the chiplets, without risking adjacent temperature sensitive layers, whilst maintaining a post-bond misalignment specification of 2.5 um in X and Y. In addition, with further optimization of the bonding profile in incidence time, temperature and profile and an understanding of the heat transfer through the wafer stack, we can begin to identify best practices for dealing with components with strict thermal budgets, whilst maintaining a reasonable device throughput. The resulting high-performance RF silicon interposer platform integrated with InP chiplets shows reflection values less than -15 dB in the 110 – 170 GHz range and the average bonding misalignment found was less than 600 nm in both the X and Y direction and with a rotational misalignment less than 0.05° across 43 bonded devices.

In this contribution, an enhanced 3-D differential surface admittance operator is proposed, facilitating accurate modeling of piecewise homogeneous cuboidal objects. By exploiting the analytical properties of entire-domain basis functions, material interfaces are effectively eliminated from the formulation, leading to a reduction in the number of unknowns without compromising the accuracy of the operator. After a validation of the novel approach, its effectiveness is demonstrated through the analysis of the impedance responses of on-chip interdigital capacitor structures.

This paper presents an advanced RF silicon interposer platform that integrates high-Q passive components and flip- chip InP die for wideband high frequency applications. By spin coat low-loss RF polymer (CYCLOTENET XP80) on top of the thick metal redistribution Layers (RDLs) for signal routing, the platform achieves low insertion loss, excellent impedance control, and high integration density. Measured insertion losses are 0.23 dB/mm at 140 GHz, 0.5 dB/mm at 220 GHz, and 0.73 dB/mm at 325 GHz, demonstrating state-of-the-art performance. Dielectric characterization using antenna-and resonator-based methods determines a relative permittivity of approximately 2.55 (+/- 1.5%) across the 110325 GHz frequency range. An integrated InP power amplifier ( PA) on the interposer demonstrates a 3 dB bandwidth of 116-148 GHz, a peak gain of 16.3 dB, and P1dB values ranging from 13 to 15 dBm, with a poweradded efficiency (PAE) of 15-28% within the 125-135 GHz range. Furthermore, a strong correlation between thermal sensor measurements and FEM simulations enables the extraction of XP80's thermal conductivity, which is essential for effective thermal management. These results underscore the advancement of a state-of-the-art RF interposer platform optimized for heterogeneous integration in mmWave and sub-THz applications.

Accurate modeling of on-chip passive components is vital for reliable integrated circuit (IC) design. However, this is non-trivial due to the inherent heterogeneity of the structures and the wide range of material parameters involved. In this work, we present a single-source boundary integral equation (BIE) for modeling on-chip interconnects and passive elements. To reduce the number of discretization elements—and thus the number of unknowns—we construct a 3-D differential surface admittance (DSA) operator for piecewise homogeneous cuboidal and rectilinear polyhedral objects. Specifically, a novel method is proposed to handle material interfaces efficiently. By combining this new formulation of the DSA operator with the augmented electric field integral equation (EFIE), we obtain a framework that enables accurate modeling and fast broadband impedance extraction of on-chip structures. The proposed approach is validated through several numerical experiments, including important applications such as metal-insulator-metal (MIM) capacitors, and demonstrates excellent agreement with reference solutions while significantly reducing computational cost compared to state-of-the-art solvers.

We introduce the processing of CYCLOTENE (TM) XP80 from Dupont, a new non-PFAS photo imageable dielectric (PID) with low dielectric constant (D-k) and low loss tangent (D-f) up to 140 GHz, for beyond 5G RF silicon interposers. The total target thickness of this PID in the interposer's stack, featuring three thick redistribution layers (RDL), is 29 mu m. The required curing temperature of this PID is maximum 200 degrees C for 1 hour, which is lower than other well-known low RF loss polymers such as Benzocyclobutene (BCB). This lower curing temperature led to a total warpage of about 330 mu m for a wafer size of 300 mm without any stress compensation layers. The final warpage was successfully reduced to 230 mu m by depositing a backside stress compensation layer. No delamination was detected in the thick polymer stack after compensation. An excellent RF performance with insertion loss of around 0.3 dB/mm at 110 GHz has been obtained which is comparable to BCB but with lower stress in the stack and higher integration density in comparison to PCB and glass interposers.

Electrochemical water-electrolysis for hydrogen generation often requires more energy due to the sluggish oxygen evolution reaction (OER). This work introduces a double-layered nanoflower catalyst, NiFe-LDH@S-NiFeOx/NF, featuring a crystalline NiFe-LDH coating on amorphous S-NiFeOx on nickel foam. Strategically integrating a crystalline-amorphous (c-a) heterostructure leverages strain engineering to enhance OER activity with low overpotentials (eta 100 = 220 and eta 500 = 245 mV) and stability (135 h at eta 100 and 80 h at eta 500). Theoretical density functional theory (DFT) calculations reveal that the compressive strain can optimize the adsorption of oxygen-containing intermediates to reduce the reaction energy barrier, thus improving the reaction kinetics and performance of OER. Moreover, its phosphated derivative, NiFeP@S-NiFeOx/NF, exhibits high hydrogen evolution reaction (HER) performance (eta 10 = 64 mV, eta 100 = 187 mV). An alkaline water-electrolysis cell of NiFeP@S-NiFeOx/NF(-)||NiFe-LDH@S-NiFeOx/NF(+) requires only a cell voltage of 1.77 V at 100 mA cm-2, demonstrating excellent stability over 110 h (at both 10 and 100 mA cm-2). This work highlights the benefits of integrating crystal-amorphous interfaces and strain effects, offering insights into the understanding and optimizing catalytic OER mechanism and advancing water-electrolysis technology.

Wafer-to-wafer hybrid bonding allows for the integration of different semiconductor materials and the creation of complex 3D structures, resulting in higher device density and reduced interconnect parasitic. This paper focuses on the RF performance of the interconnect in hybrid bonded devices. Specifically, we study noise coupling between 5/5μm TSVs, as well as inductive links between different metal layers and their applications for both wireless communication and non-invasive wafer testing. The study combines experimental measurements with calibrated HFSS models up to 67 GHz. ESD tests have also been conducted on hybrid-bonded inductor loops for reliability evaluations.

Retrieval finds a small number of relevant candidates from a large corpus for information retrieval and recommendation applications. A key component of retrieval is to model (user, item) similarity, which is commonly represented as the dot product of two learned embeddings. This formulation permits efficient inference, commonly known as Maximum Inner Product Search (MIPS). Despite its popularity, dot products cannot capture complex user-item interactions, which are multifaceted and likely high rank. We hence examine non-dot-product retrieval settings on accelerators, and propose mixture of logits (MoL), which models (user, item) similarity as an adaptive composition of elementary similarity functions. This new formulation is expressive, capable of modeling high rank (user, item) interactions, and further generalizes to the long tail. When combined with a hierarchical retrieval strategy, h-indexer, we are able to scale up MoL to 100M corpus on a single GPU with latency comparable to MIPS baselines. On public datasets, our approach leads to uplifts of up to 77.3% in hit rate (HR). Experiments on a large recommendation surface at Meta showed strong metric gains and reduced popularity bias, validating the proposed approach's performance and improved generalization.

A novel technique to accurately characterize interconnects with general, piecewise homogeneous material parameters and arbitrary polygonal cross sections is presented. To compute the per-unit-of-length (p.u.l.) complex inductance and capacitance matrices of the considered structures, we apply a boundary integral equation (BIE) framework, invoking a Dirichlet-to-Neumann (DtN) formalism to recast the problem at hand. The pertinent operators are constructed by means of the numerically fast Fokas method, leveraging fully analytical expressions for the pertinent matrix elements. Numerical examples of various multiconductor transmission lines demonstrate that our proposed scheme is flexible and precise. Since our method is not limited to rectangular cross sections, manufacturing effects such as etching can also be taken into account. Moreover, the examples are not restricted to resistance, inductance, conductance and capacitance (RLGC) data as we also consider signal attenuation, slow-wave factors, and crosstalk.

In state-of-the-art interconnect design, topologies including magnetic materials, such as the so-called superlattice conductors, are rapidly emerging as a novel strategy to handle the challenges associated with the evolution toward higher operating frequencies and integration densities. Consequently, it is imperative that the newly developed full-wave electromagnetic solvers rigorously model these innovative materials and still accurately capture phenomena such as the skin and proximity effect in good conductors. In this article, we propose such a method to rigorously characterize this important class of interconnects with arbitrary, possibly frequency-dependent, material properties, including combined dielectric and magnetic contrast. To that end, a 2-D differential surface admittance (DSA) operator is used, which invokes a single-source equivalence theorem to model both nonmagnetic and magnetic conductors efficiently. This operator is combined with the electric field integral equation (EFIE), yielding a comprehensive formalism to extract the pertinent per-unit-of-length (p.u.l.) resistance and inductance parameters of the modeled structures. The numerical properties of our technique are studied in detail, with particular attention to the influence of magnetic materials. Finally, various relevant application examples are considered to establish its correctness and versatility.

In this contribution, we propose a novel approach to rigorously model interconnect structures with an arbitrary convex polygonal cross-section and general, piecewise homogeneous, material parameters. A full-wave boundary integral equation formulation is combined with a differential surface admittance approach, invoking an extended form of the numerically fast Fokas method to construct the pertinent operator. Several examples validate our method and demonstrate its applicability to per-unit-of-length resistance and inductance characterization.

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1- $\mathrm {W}/{\mathrm {mm}}^{2}$ power-density target for high-performance computing (HPC) systems, a 25-high- $Q$ -factor (300 MHz), 150- $\mu \text{m}$ -thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57- $\mu \text{m} V_{\mathrm {DD}}$ -bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10- $\mu \text{m}$ -horizontal-pitch nano- through-silicon via ( $n$ TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency $\eta \,\,=83$ % can be obtained for 1- $\mathrm {W}/{\mathrm {mm}}^{2}$ power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.

Heterogenous integration is rapidly becoming important to the future roadmap of mmwave and sub-THz communications and sensing front ends. This is driven by the need for compound semiconductors which offer significant benefits in power, efficiency and footprint. This integration however is of a different nature than that for e.g. logic-memory, leading to viable solutions using interposers or printed circuit boards (PCB). We show some recent results on both interposer and PCB, with insertion losses for interconnects of the order of 1 dB and 0.1 dB respectively for D-band applications. We highlight their benefits and the challenges still present.

In this work, we present the analytical model of buck converter with 3-D in-package air-core inductor ( $150~\mu \text{m}$ thick). To optimize the power efficiency at a targeted power density, models including 3-D inductor and power switches are developed. Compared to 3-D electromagnetic (EM) simulation, the proposed inductor model has a modeling error within 12% for the inductance calculation. With the proposed design methodology, an inductor with $Q$ -factor up to 35 at 300 MHz is achieved. From the system aspect, the loss breakdown in the integrated power converter is investigated. A 0.5 ratio buck converter can reach 88.5% efficiency at 1–5 W/mm 2 based on the optimized inductor designs, with output voltage ranging from 0.7 to 0.9 V and based on 28 nm CMOS.

We present a $\mu \text{m}$ -thin-profile power delivery solution including a charge pump with integrated passives. Targeting 1 W/mm 2 or higher power density, a 2.5-D high-density metal-insulator-metal (MIM) capacitor deposited on high aspect ratio (HAR) (up to 5) oxide studs is proposed. With approximately 25-nm-thick HfAlOx dielectric, its measured capacitance density is 25.4 nF/mm 2 for a capacitor size ranging from 1/16 mm 2 to 1 mm 2 . This shows $3.6\times $ density improvement compared with the planar MIM. Theoretically, 86 nF/mm 2 density@1.36-V bias can be obtained if a 10-nm dielectric is deposited. Moreover, the measured leakage current density is within 65 pA/mm 2 at 1-V bias (negligible for a 1 W/mm 2 -power delivery). For a backside (BS) power delivery, this 2.5-D MIM capacitor can be realized by only three BS metal layers. This enables the low-cost and thin-profile delivery system ( $\sim \!\!\mu \text{m}$ thickness), and the whole power delivery efficiency including a 1/2-ratio charge pump is $\eta \,\,=84$ %@1 W/mm 2 (>5% boost in the power efficiency).

We present a highly-scaled packaging and system-integration RF interposer platform on low-resistivity Si (15-25 Ωcm). The heterogenous platform has been processed and characterized by measurements in the frequency range from 10 MHz to 110 GHz, revealing an interconnect insertion loss less than 0.3 dB/mm at 100 GHz and Q max above 40 for integrated inductors. The excellent performance of the RF Si interposer enables high frequency interconnects between the ICs and the partial matching network in the package. The narrow pitch of the μbumps further enables flip-chip performance up to 500 GHz, allowing for heterogenous integration of multiple mm-wave ICs in different technologies, together with integrated high-Q passives, as well as antennas-in-package for RF to beyond-5G applications.

Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precisions—FP16, Hybrid-FP8 (HFP8), INT4, and INT2—to support diverse application demands for training and inference. The chip leverages cutting-edge algorithmic advances to demonstrate leading-edge power efficiency for 8-bit floating-point (FP8) training and INT4 inference without model accuracy degradation. A new HFP8 format combined with separation of the floating- and fixed-point pipelines and aggressive circuit/architecture optimization enables performance improvements while maintaining high compute utilization. A high-bandwidth ring protocol enables efficient data communication, while power management using workload-aware clock throttling maximizes performance within a given power budget. The AI chip demonstrates 3.58-TFLOPS/W peak energy efficiency and 26.2-TFLOPS peak performance for HFP8 iso-accuracy training, and 16.9-TOPS/W peak energy efficiency and 104.9-TOPS peak performance for INT4 iso-accuracy inference.

In this paper, we will discuss the progress that has been made in upscaling GaN and InP to a Si platform as well as making them CMOS and 3D compatible to enable the heterogeneous systems that will be needed for 5G mm-wave and 6G sub-THz frequencies for high-capacity wireless communication.