Metal oxide materials such as tin oxide (SnO2) show powerful gas sensing capabilities. Recently, the deposition of a thin tin oxide film at the backend of a CMOS processing sequence has enabled the manufacture of modern gas sensors. Among several potential deposition methods for SnO2, spray pyrolysis deposition has proven itself to be relatively easy to use and cost effective while providing excellent surface coverage on step structures and etched holes. A model for spray pyrolysis deposition using a pressure atomizer is presented and implemented in a Level Set framework. A simulation of tin oxide deposition is performed on a typical gas sensor geometry and the resulting structure is imported into a finite element tool in order to analyze the electrical characteristics and thermo-mechanical stress present in the grown layer after processing. The deposition is performed at 400 °C and the subsequent cooling to room temperatures causes a stress to develop at the material interfaces due to variations in the coefficient of thermal expansion between the different materials.

In order for the gas sensor devices to enjoy the miniaturization trend that has consumed much of the electronic device industry, major research in the field is undertaken. The bulky sensor devices of previous generations can not easily be incorporated into a CMOS processing sequence, because of their bulky nature and potential higher cost of production. More recently, materials such as zinc oxide and tin dioxide have shown powerful gas sensing capabilities. Among many potential deposition methods, spray pyrolysis has become a popular approach because of its ease of use and cost effectiveness. A model for spray pyrolysis deposition is developed and implemented within the level set framework. The implementation allows for a smooth integration of multiple processing steps for the manufacture of smart gas sensor devices. From the observations, it was noted that spray pyrolysis deposition, when performed with a gas pressure nozzle, results in good step coverage, analogous to a CVD process. This is mainly due to the atomizing nozzle being placed at a reasonable distance away from the wafer surface and reducing the droplets volume and mass in order to ensure they fully evaporate prior to contact with the substrate surface. A topography simulator for this deposition methodology is presented.

We present performance results of SnO2 and CuO nanowire gas sensor devices, where single and multi-nanowire device configurations have been employed in order to optimize sensor design. In particular the response to the target gases CO, H-2, and H2S has been measured in dry and humid air; both the SnO2 and CuO nanowire sensors are able to detect CO in the low ppm concentration range, which is important for environmental monitoring. The CuO multi-nanowire devices show an extraordinary high response to H2S with sensitivity in the low ppb concentration. We present our developments of CMOS technology based micro-hotplates, which are employed as platform for gas sensitive thin films and nanowires. Potential heterogeneous integration of nanowires on the micro-hotplate chips as well as an approach towards gas sensor arrays is discussed. We conclude that CMOS integrated multi-nanowire gas sensors are highly promising candidates for the practical realization of multi-parameter sensor devices for indoor and outdoor environmental monitoring.

The deposition of a thin tin oxide film allows for the manufacture of modern gas sensors. Spray pyrolysis deposition is used to grow the required thin films, as it can be seamlessly integrated into a standard CMOS processing sequence. A model for spray pyrolysis deposition is developed and implemented within the Level Set framework. Two models for the topography modification due to spray pyrolysis deposition are presented, with an electric and a pressure atomizing nozzle. The resulting film growth is modeled as a layer by layer deposition of the individual droplets which reach the wafer surface or as a CVD-like process, depending on whether the droplets form a vapor near the interface or if they deposit a film only after surface collision.

The 0.35μm HV-CMOS process technology utilizes several junctions with different doping levels and depths. This process supports complete modular 3V and 5V standard CMOS functionality and offers a wide set of HV transistor types capable for operating voltages from 20V to 120V made available with only 2 more mask adders [1]. Compared to other reported integration of photo detection functionalities in normal CMOS processes [2] or special modified process technologies [3] a much wider variety of junction combinations is already intrinsically available in the investigated technology. Such junctions include beside the standard n+ and p+ source/drain dopings also several combinations of shallow and deep tubs for both p-wells and n-wells. The availability of junction from submicron to 7μm depths enables the selection of appropriate spectral sensitivity ranging from ultraviolet to infrared wavelengths. On the other side by appropriate layouts the contributions of photocurrents of shallower or deeper photo carrier generation can be kept to a minimum. We also show that by analytically modelling the space charge regions of the selected junctions the drift and diffusion carrier contributions can be calculated with a very good match indicating also the suppression of diffusion current contribution. We present examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 380-450nm, 450-600nm or 700-900nm. By appropriate junction choice the ratios of the generated photo currents in their respective peak zones can exhibit more than a factor of 10 compared to the other photo diode combinations. This enables already without further filter implementation a very good spectral resolution for colour sensing applications. Finally the possible junction combinations are also assessed by the achievable dark current for optimized signal to noise characteristic.

Three-dimensional integrated circuits (3D ICs) introduce wafer bonding and Through Silicon Vias (TSVs) as new modules, thus extending manufacturing requirements beyond CMOS. A 3D IC with a photosensor is taken as an example to further analyze the resulting new metrology requirements for mass production. For the wafer bond module, data on defects before and after bonding, bond interface adhesion strength, and the module, thickness control for deposited layers and defect metrology including the trench sidewall and bottom are identified as key requirements. Mass production requires non-destructive inline metrology in all cases. This has been achieved for electrical parameters, bond void (Scanning Acoustic Microscopy), and TSV depth monitoring (optical methods). Other parameters such as bond strength, as well as layer thickness or defect metrology inside TSVs, demand further R&D.

The ability to deposit a thin tin oxide film on CMOS chip dies has enabled the manufacture of modern smart gas sensor devices. Spray pyrolysis deposition is used to grow the required thin films, as it is an affordable deposition technique which can be integrated into a standard CMOS processing sequence. A model for spray pyrolysis deposition is developed and implemented within the Level Set framework using Monte Carlo techniques. Two models for the topography modification due to spray pyrolysis deposition are presented, with an electric nozzle and a pressure atomizing nozzle. The resulting film growth is described as a layer by layer deposition of the individual droplets which reach the wafer surface and deposit as flat round disks or as a CVD-like process, depending on whether the droplets form a vapor near the interface or they deposit a film only after surface collision. Some additional geometries are simulated in order to analyze how the spray pyrolysis technique coats trench structures, essential for increasing the surface area of the gas sensing layer.

In 3D integration, interconnections between stacked dies are ensured by conductive through silicon vias. Electrical conduction is achieved via coating the vias sidewalls with a metal, such as tungsten. In this work we have compared thermal-dependent stress of thin tungsten films deposited either in full plate oron vias sidewalls. The comparison of stress measurements at room temperature and during heating cycles reveals large differences between full plate and vias samples. At room temperature, in the vias samples, the stress is a factor 4 less than it is in the full plate sample, with both values indicating a tensile stress. While a thermo-elastic behavior is expected for the full plate sample, no stress evolution as a function of temperature is observed in the case of the vias samples.

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.

Integration of thin tin oxide film formation into CMOS technology is a fundamental step to realize sensitive smart gas sensor devices. Spray pyrolysis is a deposition technique which has the potential to fulfil this requirement. A model for spray pyrolysis deposition is developed and implemented within a Level Set framework. Two models for the topography modification due to spray pyrolysis deposition are presented, with an electric and a pressure atomizing nozzle. The resulting film growth is modeled as a layer by layer deposition of the individual droplets which reach the wafer surface or as a CVD-like process, depending on whether the droplets form a vapor near the interface or if they deposit a film only after surface collision.

The development of smart gas sensor devices for daily life application requires considerable technological efforts related to CMOS integration of gassensitive materials. We are focusing on the heterogeneous integration of ultrathin (50nm) SnO2 layers deposited by spray pyrolysis with CMOS devices. With respect to miniaturization and implementation of the sensing layers on micro-hotplates (μhps) we compared the H2 responses for 100x100μm2 and 5x100μm2 sized sensing films and found a very high response of 42% and 28%, respectively, for 10ppm H2. We performed 2-point and 4-point electrical measurements of SnO2 layers on typical CMOS Al contacts and achieved linear V-I characteristic in the full operating temperature range up to 350¡C in 4-point configuration. We also demonstrate the excellent step coverage of the deposited SnO2 layers on passivated CMOS chips, which is highly important for post-CMOS processing of the sensor films.

In this paper, investigations on absolute temperature measurements using IR-Thermography of CMOS integrated micro-hot-plates (mu HP) are presented. The results of using two different approaches, emissivity correction and black paint coating, are presented and compared with respect to simulation and electrical testing results. In addition, FIB/SEM investigations were used for surface investigations and determination of possible influences to the thermal behaviour by black paint coating process.