This study examined the palladium (Pd)-nickel (Ni) alloy films' ability to detect hydrogen (H2) at various Ni concentrations. The co-sputtering method was used to make the Pd-Ni alloy sensors. The response of the Pd-Ni alloys sensor reduced linearly as Ni8% concentration was added to Pd, and the resistance of the Pd-Ni alloys was reversible upon exposure to H2 gas with absorption and desorption characteristics. The experimental findings demonstrated that the Pd-Ni alloy sensor response time of 11 s was much faster than that of pure Pd, with great selectivity and stability for a period of 90 days.(c) 2022 Hydrogen Energy Publications LLC. Published by Elsevier Ltd. All rights reserved.

The large area wire grid polarizers (LA-WGPs) with 50 nm half-pitch were fabricated using ArF immersion lithography overcoming the limit of the shot field size. To realize the 50 nm line and space patterns on a 300 mm wafer, a zero-distance stitching process that connects the shot fields is suggested. To compensate for mutual interference between the shot fields which is called the local flare effect (LFE), the shot field arrangement is changed with optical proximity correction (OPC). Using a master wafer produced by the suggested method, 300 mm large-area WGPs were fabricated by the nano-imprint process. The WGPs have more than 80% transmittance in the visible light region, and the possibility of performance improvement can be confirmed depending on the number and method of the etch process.

This study analyzes the response time, that is, thermal time constant of an uncooled amorphous silicon (a-Si) infrared (IR) microbolometer cell based on simulation when the device is downscaled for higher resolution. For accurate analysis, an 80x80 array of a-Si microbolometer was fabricated with a 35 mu m pixel size. The real device was used to extract the external environmental parameter for the simulation where temperature coefficient of resistance (TCR) of a-Si is also modeled to include temperature-dependence. It is known qualitatively that the cell geometries like as the length of the resistance layer and width of the leg are key factors for the time constant of the device. When the pixel is downscaled to 17 mu m, the time constant is found to increase as the length of the resistance layer becomes narrower, but this tendency is reversed for the width of the leg. This is because the influence of each component on the total resistance is changed according to the cell area, which is efficiently optimized by the simulation analysis.

A flexible Si complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) with multi-level interconnects is realized by thinning down and transferring the CMOS IC onto a polymer substrate. A detailed mechanical and electrical reliability analysis of the flexible Si CMOS IC is carried out in relation to the neutral mechanical plane (NMP) that is extracted from both analytical and numerical modeling. To enhance the reliability by optimizing the NMP position, the thicknesses of all the layers in the CMOS IC on the polymer substrate are carefully adjusted. The NMP-optimized flexible Si CMOS IC maintains its mechanical and electrical stability even at a 5-mm radius bending condition. In addition, to explore the degradation mechanism of the flexible Si CMOS IC, the change of the interface state density of the flexible Si CMOS at different bending conditions is investigated using the charge pumping method. Finally, the long-term electrical reliability of this flexible Si CMOS IC is also investigated.

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Low-frequency (LF) noise in a vertically stacked nanowire (VS-NW) memory device, which is based on the silicon-oxide-nitride-oxide-silicon(SONOS) configuration is characterized in two different operational modes, an inversion-mode and a junctionless-mode (JM). The LF noise showed 1/f-shape behavior regardless of the operational mode and followed the carrier number fluctuation model. With regard to the device-to-device variation and quality degradation of the LF noise after iterative program/erase operations, the five-story JM SONOS memory showed comparatively high immunity arising from its inherent bulk conduction and no-junction feature. Despite the harsh fabrication condition used to construct five-story VS-NW, even the five-story JM SONOS memory exhibited LF noise characteristics comparable to those of one-story JM SONOS memory. Thus, the five-story JM SONOS memory is attractive due to its high-performance capabilities and good scalability.

A gate-all-around (GAA) field effect transistor with vacuum gate dielectric is presented as a structure free from hot-carrier injection and bias temperature instability. A conventional GAA fabrication process is used along with selective removal of the sacrificial gate oxide as an extra process step. The lowered dielectric constant in vacuum gate dielectric can be compensated by the nature of the nanowire and physical oxide thickness reduction. As the nanowire channel is fully surrounded by empty space, reliability issues relevant to the gate dielectric can be completely cleared.

Co-fabrication of a nanoscale vacuum field emission transistor (VFET) and a metal-oxide-semiconductor field effect transistor (MOSFET) is demonstrated on a silicon-on-insulator wafer. The insulated-gate VFET with a gap distance of 100 nm is achieved by using a conventional 0.18-μm process technology and subsequent photoresist ashing process. The VFET shows a turn-on voltage of 2 V at a cell current of 2 nA and a cell current of 3 μA at the operation voltage of 10 V with an ON/OFF current ratio of 10 4 . The gap distance between the cathode and anode in the VFET is defined to be less than the mean free path of electrons in air, and consequently, the operation voltage is reduced to be less than the ionization potential of air molecules. This allows the relaxation of the vacuum requirement. The present integration scheme can be useful as it combines the advantages of both structures on the same chip.

For the system on panel applications, we fabricated and analyzed the polycrystalline silicon (poly-Si) silicon-oxide-nitride-oxide-silicon (SONOS) memory device on different buffer layer such as oxide or nitride. The threshold voltage (VT) and transconductance (gm) are extracted from each device and the X-Ray Diffraction (XRD) measurement is carried out to interpret these characteristics. The results show the device on oxide layer has higher mobility and lower VT than on nitride layer. From the XRD spectra, it can be explained by the fact that the grain size of poly-Si on oxide layer has larger than on nitride layer. The both devices show program/erase characteristics as the potential of SOP memory devices.

Nanoelectromechanical (NEM) switches 1 , 2 , 3 , 4 , 5 , 6 have received widespread attention as promising candidates in the drive to surmount the physical limitations currently faced by complementary metal oxide semiconductor technology. The NEM switch has demonstrated superior characteristics including quasi-zero leakage behaviour 1 , excellent density capability 2 and operation in harsh environments 3 . However, an unacceptably high operating voltage (4–20 V) has posed a major obstacle in the practical use of the NEM switch in low-power integrated circuits. To utilize the NEM switch widely as a core device component in ultralow power applications 7 , 8 , 9 , 10 , 11 , the operation voltage needs to be reduced to 1 V or below. However, sub-1 V actuation has not yet been demonstrated because of fabrication difficulties and irreversible switching failure caused by surface adhesion. Here, we report the sub-1 V operation of a NEM switch through the introduction of a novel pipe clip device structure and an effective air gap fabrication technique. This achievement is primarily attributed to the incorporation of a 4-nm-thick air gap, which is the smallest reported so far for a NEM switch generated using a ‘top-down’ approach. Our structure and process can potentially be utilized in various nanogap-related applications, including NEM switch-based ultralow-power integrated circuits, NEM resonators 12 , 13 , nanogap electrodes for scientific research 14 and sensors 15 .

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide. (C) 2013 Elsevier Ltd. All rights reserved.

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage (VT) shift of 2.5 V in 1ms using a gate pulse of + 14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

This paper discusses the 3-level charge pumping method in planar-type Silicon-Oxide-High-k-Oxid e-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason for degradation of data retention properties. In the CP thechnique, a pulse is applied to the gate of the MOSFET which alternately fills the traps withe electrons and holes, thereby causing a recombination current Icp to flow in the substrate. A 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices were fabricated from polycrystalline silicon (poly-Si) using the solid phase crystallization (SPC) method for use in a low-power system-on-panel (SOP) display. In these poly-Si SONOS memories, oxide or nitride was used as a buffer layer. The electrical characteristics, such as the threshold voltage (V (T) ), subthreshold slope (SS) and transconductance (g (m) ), were determined for each SONOS device. To interpret the characteristics of both poly-Si devices, x-ray diffraction (XRD) measurements and flicker noise analysis were conducted. The results show that the poly-Si SONOS on the oxide layer has better electrical, memory characteristics, such as turn-on speed and g (m) , program/erase, endurance and data retention than that on the nitride layer. From the XRD measurements, it is shown that the grain size of the poly-Si on the oxide layer is larger than that on the nitride layer. From the flicker noise analysis, the poly-Si device on oxide was shown to have less traps or defects in the channel layer than that on nitride.

In this paper, a new body engineering structure for ZnO thin-film transistors (TFTs), a Schottky-contact-merged (SCM) ZnO TFT, is proposed, in which the Schottky contact is formed on the body of the ZnO TFT to improve the electrical characteristics without requiring an additional mask and process. In a conventional bottom-gate ZnO TFT, the I–V characteristics usually show a negative-shifted turn-on voltage (V ON) with a large subthreshold slope (SS). By adapting the suggested structure, V ON could be shifted from−13 to−4.4 V with the additional improvement of SS from 1.5 to 0.48 V/decade. In addition, the SCM structure has better electrical stability, which means that it allows for better control of the charge trapping during bias operations.

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of N-2 ion implantation (N-2 I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage (VT) of 0.13 V, and a higher g(m. max) of 18.6 mu A/V and mobility of 27.02 cm(2)/Vs than the conventional and N-2 I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and N-2 I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.