To mitigate the constraint of the increased gate resistance for dual-workfunction-gate (DWG) cell transistors as a standard platform in the DRAM industry, a Middle-silicon- TiN Gate (MSTG), which replaces the n+-polysilicon with an ultra-thin TiN/silicon interlayer/bulk TiN was demonstrated in a fully integrated 1x-nm 16Gb, and provides superior retention time (2 times) without sacrificing the gate resistance compared to those of the single workfunction gate (SWG). (Keywords: dual-workfunction-gate, gate resistance, TiN, silicon interlayer, retention time, GIDL)

A highly biased linear current method (HBLCM) for separately extracting source and drain resistance (R-S and R-D) in MOSFETs is proposed. The technique can be applied to a single device by using simple modeling. Compared to other methods, it provides accurate values of R-S and R-D because it considers carrier mobility degradation. The method basically uses linear current versus gate voltage (I-DS-V-GS and I-SD-V-GD) characteristics before and after the source/drain interchange (I-DS and I-SD). Afterward, by using the traditional Y-function and subsequent resistance modeling in a highly biased linear condition, R-S and R-D can be separately extracted. In order to evaluate and verify the accuracy of HBLCM, an external resistor was intentionally connected to a source electrode of a device, and the resulting change in source resistance was detected using the proposed method. Moreover, to demonstrate an application of the proposed method, internal resistance deliberately created by hot-carrier injection (HCI) was linked to a drain electrode, thereby changing drain resistance. The changed drain resistancewas also sensed by the HBLCM. Afterward, the HCI-stressed device was cured by electrothermal annealing driven by Joule heating, and the recovery was again clearly observed using the proposed method.

We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H-2) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.

We report an accurate extraction technique of effective mobility (mu(eff)) by considering gate-bias (V-GS) dependent effective inversion charges (Q(inv,eff)) as a normalized correction factor (sigma(V-GS)) when using the gate-to-source/drain capacitance-voltage (C-V) measurement in a p-channel Si/SiGe MOSFET with a floating body structure. In the proposed technique, two different capacitance-voltage configurations: a gate-to-source/drain (CG-SD) configuration without body contact and a gate-to-source/drain/body (CG-SDB) configuration with body contact are utilized for the accurate extraction of mu(eff).

The Vt variation of TiN-metal buried-gate (BG) cell transistors in DRAM is characterized. The use of TiN gate shows a large Vt variation and is attributed to the formation of chlorine (Cl)-related trap sites during the etch-back process of the metal gate. This indicates that the Cl component in the chemical vapor deposition (CVD) process of the TiN gate is responsible for such a phenomenon. Reduction of the Vt variation is achieved by rapid thermal annealing (RTA) after the etch-back process.

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D it). It is worthwhile to note that the D it as well as the GIDL current is a still meaning parameter to analyze the data retention time.

Adeviceplatformwithnanochannels,fabricatedbyeithertopdown or bottom-up nanofabrication technologies, has been attracting notable attention in various fields and applications. Asarepresentativecaseofsuchnanochanneldeviceplatform,a nanogap- embedded field-effect-transistor (FET) has shown a great potential as a fast and label-free detection tool for a specific target material by monitoring the changes in electrical characteristicssuchasthethresholdvoltageorconductivity. [1,2] In a recent publication, for example, we reported that the nanogap-embedded FET can detect biomolecules in a very sensitive way by confining them within the nanogap and by monitoring the induced change in the effective dielectric constant of gate dielectrics, which is directly tied to the threshold voltage of the FET under study. [1] Alternatively, a conductivity change that was induced upon bridging the gap with a conductive nanomedium was used as an unlabeled biosensor. [3,4] Inthosedevices,itisoftendifficulttoconfirmina

Gold nanoparticle (GN) embedded silicon nanowire (SiNW) configuration was proposed as a new biosensor for label-free DNA detection to enhance the sensitivity. The electric current flow between two terminals, a source and a drain electrode, were measured to sense the immobilization of probe oligonucleotides and their hybridization with target oligonucleotides. The complementary target oligonucleotide, breast cancer DNA with 1 pM, was sensed. In addition, its sensing mechanism and limit of detection (LOD) enhancement was investigated through simulation. The results support that the LOD can be improved by reducing the SiNW doping concentration. This emerging architecture combined nanostructure of spherical GN and SiNW has high potential as a label-free biosensor due to its facile fabrication process, high thermal stability, immobilization efficiency with a thiol-group in a self-assembled monolayer (SAM), and improved sensitivity.

Unified random access memory (URAM) with a separated double-gate is demonstrated on a fully depleted polysilicon (poly-Si) thin-film-transistor (TFT) template. Integration of a front-gate dielectric of tunneling oxide/nitride/control oxide (O/N/O) and a floating poly-Si channel provides the two versatile functions of nonvolatile silicon oxide-nitride oxide-semiconductor Flash memory and high-speed capacitorless single-transistor 1T-DRAM in a single transistor. In this design, the memory mode of URAM is selected according to user specifications. As the back-channel is assigned for capacitorless 1T-DRAM while the front-channel is devoted for Flash memory, spatial separation minimizes undesired soft programming in the front O/N/O layer and allows for capacitorless 1T-DRAM operation irrespective of the data state of the nonvolatile memory. This feature presents interference-free operation between the two modes. In addition, the virtue of the TFT process allows the potential for stackable memory for ultra-high-density era.

With a simple and conformal metal nanocrystal dipping of synthesized micelles, nonvolatile memory characteristics originating from a metallic cobalt (Co) core nanocrystal (NC) surrounded by a Co-oxide shell are investigated in this study. From transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS), it was confirmed that Co-oxide was made by oxygen plasma for polymer oxidation and that metallic Co wrapped with a Co-oxide shell was made by hydrogen annealing in order to reduce the Co-oxide. Energy band diagrams considering the extent of the coexistent metallic Co/Co-oxide were also analyzed in terms of how they correspond to each program/erase/retention case. These cases were verified by electrically measured data. These results can provide a guideline for the design and optimization of metal NC embedded memory.

2010 International Conference on Solid State Devices and Materials,A Study of a Data Retention Characteristic for Various Schemes of Gate Oxide Formation in Sub-50-nm Saddle-Fin Transistor DRAM Technology

We report the synthesis of free-standing MnSi nanowires via a vapor transport method with no catalyst and measurements of their electrical and magnetic properties for the first time. The single-crystalline MnSi nanowire ensemble with a simple cubic (B20) crystal structure shows itinerant helimagnetic properties with a T(c) of about 30 K. A single MnSi nanowire device was fabricated by a new method using photolithography and a nanomanipulator that produces good ohmic contacts. The single-nanowire device measurements provide large (20%) negative magnetoresistance and very low electrical resistivity of 544 microOmegacm for the MnSi nanowire.

This paper investigates how gate height (H,), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a IT-DRAM operation. A device with a lower H. yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower H, shows slightly poor retention characteristics in the NVM unlike the IT-DRAM.

A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n+ front gate and p+ back gate) shows a wider sensing current window than a symmetric double gate (n+ front gate and n+ back gate). This is attributed to the inherent flatband voltage between the p+ back gate and the channel inducing a deeper potential well, which allows capacitorless 1T-DRAM operation at a low back-gate voltage. The TFT capacitorless 1T-DRAM can be applied for future stackable memory for the ultrahigh density era.

A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized according to the designer's demand. With the utilization of the impact ionization method for 1T-DRAM programming, undesired soft charge trapping into O/N/O gradually shifts the threshold voltage, resulting in an unstable operation in the URAM. In order to avoid such problems associated with soft programming, a gate-induced drain-leakage (GIDL) program method is proposed for improved immunity to disturbance. It is found that the GIDL method effectively suppresses soft programming without sacrificing the sensing current window.

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si1-yCy substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered Si1-yCy substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.

A one-transistor nonvolatile SRAM (ONSRAM) on a silicon nanowire (SiNW) SONOS is demonstrated. A nonvolatile memory (NVM) property is attained by employment of O/N/O gate dielectric stacks as an electron storage node, and SRAM functionality is achieved by exploiting latch phenomena of a floating body in SiNW. Abrupt inverter switching, superior sensing current (≥21µA), and robust interference immunity between SRAM and NVM verify the feasibility for the suggested ONSRAM.

The isolation-dielectric effects of a FinFET structure with a partially depleted (PD) silicon-on-insulator (PDSOI) region as a charge storage node on the characteristics of 1T-DRAM are reported in this brief. By introducing the low-permittivity isolation dielectric as an isolation layer among the active regions, the body potential over the PDSOI region is reduced due to the decreased capacitive coupling between the gate and the PD region; hence, it yields a widened 1T-DRAM sensing margin despite high off-state and low on-state currents. The increased gate height shows the high sensitivity of the sensing margin through the isolation-dielectric permittivity in the PDSOI FinFET 1T-DRAM.

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si1-yCy substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered Si1-yCy substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.