GaN p-channel field-effect transistors (p-FETs) are critical for enabling complementary integration of power and logic, while offering high breakdown capability. However, achieving high on-current in GaN p-FETs remains a significant challenge, primarily due to the low hole concentration, poor mobility, and challenges in forming stable, low-resistance ohmic contacts. Here, we present a novel GaN p-FET architecture that exhibits unconventional electron conduction, which helps enhance both thermal response and current modulation. We conduct a comprehensive investigation of heavily Mg-doped p++-GaN layers, focusing on contact optimization for high-temperature operation. Structural and interfacial characterization confirms high crystal quality and a thermally robust Ni/Au contact stack stabilized by an interfacial NixOy layer. This strategic interfacial layer, combined with moderate-temperature annealing, promotes Mg activation and suppresses oxygen-related traps, resulting in a ~ 73% reduction in contact resistance. Temperature-dependent analysis further reveals non-monotonic Schottky barrier modulation driven by interface evolution. Integrated into the device, this contact strategy enables thermally enhanced operation, with a drastically increase in on-state current and threshold voltage shifting positively by ~ 69% with temperature. These findings highlight a model shift in GaN p-FET design, where interface study and transport-mode innovation enable high-performance, thermally resilient devices for next-generation power integration.

Today, global electrification requires new materials for power applications. 4H-SiC dominates the market due to its excellent energy efficiency and wide operating range. This study explores the formation of Ni/4H-SiC backside ohmic contacts using 308 nm nanosecond laser annealing (NLA). After depositing an 80 nm layer of Ni onto 4H-SiC wafers through sputtering, different laser annealing parameters were tested. The energy densities (ED) ranged from 2.4 to 5.4 J cm-2, the number of laser pulses applied varied from 1 to 20, and the chuck temperatures from 25 to 400 degrees C. For all series, a common scenario was observed as a function of ED, with initial solid state reactions, then local melting, and finally complete melting and dewetting of the top layer at high ED. An in-depth understanding of the effect of laser conditions on these stages is proposed based on electrical data, Raman spectroscopy, optical microscopy, scanning electron microscopy and transmission electron microscopy cross analysis. Increasing the pulse number and using a heated chuck can substantially lower the energy density (ED) necessary to achieve low-resistance contacts. In addition, trends in sheet resistivity and contact resistivity are related to microstructural evolution during NLA exposure. A contact resistivity of around 5 x 10-5 Omega.cm2 is obtained when the wafer is processed at 25 degrees C. It drops to 10-5 Omega.cm2 when processed at 400 degrees C.

In this work, we investigate the static electrical parameters of 1200 V 4H-SiC power diodes with various designs and architectures (Schottky, PiN, and JBS with hexagonal or stripes anode), fabricated on two types of 150 mm substrates (single crystal 4H-SiC reference and 3C-poly silicon carbide based substrates: SmartSiCTM). I(V) measurements are carried out in both reverse and forward modes to assess the impact of designs and substrates. Non-destructive avalanche mode is reached with similar performance (leakage, VAV) observed for both substrates (due to identical drift layers and device structures). All diode designs on SmartSiCTM exhibit a larger current conduction and less resistance in the ohmic regime (compared to bulk), whatever the temperature (up to 200°C). Partitioning model is also proposed for evaluating the substrate contribution on the measured specific resistance and on the observed SmartSiCTM gains.

This study investigated the low contact resistivity and Schottky barrier characteristics in p-GaN by modifying the thickness and doping levels of a p-InGaN cap layer. A comparative analysis with highly doped p-InGaN revealed the key mechanisms contributing to low-resistance contacts. Atomic force microscopy inspections showed that the surface roughness depends on the doping levels and cap layer thickness, with higher doping improving the surface quality. Notably, increasing the doping concentration in the p++-InGaN cap layer significantly reduced the specific contact resistivity to 6.4 ± 0.8 × 10−6 Ω·cm2, primarily through enhanced tunneling. Current–voltage (I–V) characteristics indicated that the cap layer’s surface properties and strain-induced polarization effects influenced the Schottky barrier height and reverse current. The reduction in barrier height by approximately 0.42 eV in the p++-InGaN layer enhanced hole tunneling, further lowering the contact resistivity. Additionally, polarization-induced free charges at the metal–semiconductor interface reduced band bending, thereby enhancing carrier transport. A transition in current conduction mechanisms was also observed, shifting from recombination tunneling to space-charge-limited conduction across different voltage ranges. This research underscores the importance of doping, cap layer thickness, and polarization effects in achieving ultra-low contact resistivity, offering valuable insights for improving the performance of p-GaN-based power devices.

Power semiconductor devices are constructed to endure high voltages (>30 V) and manage high current density. Edge termination is a specific feature that must be integrated into the device architecture to achieve high voltage capability in vertical power components. It is necessary to design these edge terminations while taking into account the device's architecture and technology. Termination efficiency is the main factor, but its area is also of great significance. Many edge termination designs with efficiency close to 100 % have been reported and are currently used in commercial devices. However, having a near-100 % static breakdown voltage is not the only requirement in modern power devices. Today, most power applications rely on the avalanche capability as a key parameter. Avalanche capability is defined by the device ability to enter in non-destructive avalanche mode, where the component can temporarily sustain a high voltage and a high current in blocking mode. The Unclamped Inductive Switching (UIS) test can be used to measure the avalanche mode, and it can be customized to define a safe operating area for a full avalanche mode (SOA). The safe operation of both single pulse and repetitive pulsed avalanche limits can be characterized. Such operation mode is now controlled in both Silicon and Silicon Carbide based power devices. However, the development of novel wide and ultra-wide band gap semiconductors in regards to avalanche capability and SOA still require a lot of work.

On-wafer measurements of 1200V rated 4H-SiC power diodes have been performed in near avalanche mode to investigate the stability and robustness of the devices. The method consists of biasing the SiC diodes at near-avalanche current or voltage levels for a variable period of time. The drifting of the static electrical parameters (leakage current, avalanche voltage, Schottky barrier height) is then studied. For two different SiC diode processing technologies, two drift behaviors of the blocking I-V curves were observed. Impact ionization, which is responsible for the avalanche phenomenon at high electric fields, has been localized and distinguished between the active region of the devices and the edge termination region, depending on the processing technology. Electroluminescence observations and numerical simulations were performed to confirm the interpretation of the electrical results. The robustness of the method was further supported.

The fast-growing market of GaN-based power electronics requires the development of performing ohmic contacts. The Ti/Al stack, being one of the most popular, has been thoughtfully investigated over the years in terms of electrical performances but remains to be better understood in terms of contact formation and related solid-state reactions, especially when targeting small Ti to Al ratios (typically, down to lower than 5 at. %). In this paper, the influence of the deposited Ti layer thickness on the resulting contact is investigated using in-situ and ex-situ XRD methods as well as TEM imaging. It is found that a threshold exists, below which the diffusion phenomena ruling alloy formation during annealing are controlled, leading to a frozen Al3Ti/Al bi-layer morphology. Past this threshold, the erratic formation of non-textured Al3Ti grains is observed, which is detrimental to devices performances. The result interpretation is supported by an extended bibliography survey focused on material science, the first of the sort.

In this paper, we present a general overview of AIGaN/GaN MOS channel High Electron Mobility Transistor (HEMTs) with fully recessed gate architecture fabricated on 200mm Si-wafer. Specifically, an insight on its benefits compared to market competitors is brought out respectively from transistor electrical characteristics to robustness behavioral aspects.

Today, wide bandgap (WBG) GaN semiconductors are considered the future, allowing the improvement of power transistors. The main advantage of GaN is the presence of two-dimensional electron gas (2Deg) typically used as a conduction layer in normally-on and normally-off transistors. Concerning the normally-off family, several solutions are proposed. Among these, one of the most promising is the MIS-Gate technology that features a gate recess architecture allowing the semiconductor to physically cut off the 2Deg and drastically decrease gate–source leakage currents. The Vth relaxation characteristic, after voltage stress, has been investigated. It has been shown that the main impact is due to charges close to the gate dielectric/GaN interface, precisely dwelling within the dielectric or the GaN epitaxy. This work provides an analytical model of the Vth evolution of these MIS-GATE (metal insulator semiconductor gate) transistors fabricated on GaN-silicon substrate. This model allows the extraction of different trap energy levels from a temporary threshold voltage (Vth) shift after 650 V stress. Based on this method, it is possible to identify up to four different trap energy levels. By comparing state of the art methods, we show that these obtained energy levels are well correlated with either magnesium and carbon impurity or Ga and/or N vacancy sites in the GaN epitaxy.

We present an access technology suitable for scaled gallium nitride (GaN) high electron mobility transistor (HEMT) in Ka-band. The comparison between OFF-state characteristics of a silicon implant-assisted contact and a conventional recessed Ti/Al-based Ohmic contact is presented. The transistor with source/drain extension by Si implantation has a low contact resistance with ${R}_{C}$ down to $0.4 ~\Omega \cdot {\mathrm {mm}}$ and a sheet resistance of the implanted layer of $67~ \Omega $ /sq. In addition to promising contact performance, transistors with source and drain extension sustain high breakdown voltage (BV) with short dimensions for high-frequency applications. The systematic study of gate–source, gate–drain, and gate length variations shows a new breakdown mechanism for implanted access technology with current flowing beneath the channel leading to an unusual correlation between source–drain spacing and BV. With a conventional titanium-alloyed contact, a punchthrough effect is responsible for the BV. Cross-sectional transmission electron microscopy and secondary ion mass spectroscopy (SIMS) characterizations on both wafers highlight a degradation of the AlGaN-based back-barrier and a high silicon concentration deep into the epitaxial stack on the implanted wafers indicating a way to improve BV with an adapted process flow.

In this paper we present a detailed performance status of AlGaN/GaN MOS channel High Electron Mobility Transistors (MOSc HEMTs) with fully recessed gate architecture on 200mm Si substrates. We report a wide range of wafer and package level results. ON state resistance is studied through three aspects: i) RON partitioning with analysis of its four components, ii) RON temperature dependence, iii) cumulative dynamic RON under stress. For accurate power assessment we characterize packaged devices and compare the typical figures of merit (gate charge, switching tests) to state of the art references (especially pGaN gate HEMTs). We highlight the benefits offered by this technology for 650V applications, such as very low I GSS leakage even at 150°C, and better switching performances, t d(on) , t d(off) .

In this study, we investigate the difference between ID(VG) and C(VG) pBTI shifts on GaN-on-Si E-mode MOS-channel HEMTs, under various gate voltage stresses (VGStress) and temperatures (T). A new experimental setup using ultra-fast and simultaneous ID(VG) and C(VG) measurements enables to monitor the threshold voltage VTHdrift through two metrics, $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$. Experimental pBTI results depict a difference between $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$, such as $\mathrm{\Delta}\mathrm{V}_{\text{THI}} < \mathrm{\Delta}\mathrm{V}_{\text{THC}}$. TCAD simulations support that ID(VG) shift ($\mathrm{\Delta}\mathrm{V}_{\text{THI}}$) is related to charge trapping in Al2O3gate oxide defects at the gate corners regions while C(VG) shift ($\mathrm{\Delta}\mathrm{V}_{\text{THC}}$) is mainly ascribed to the gate bottom, due to the presence of a back-barrier layer in the epitaxy. These previous results enable to deduce that the Al2O3defects density is more important at the gate corners than at the gate bottom.

We develop a new protocol based on Y-function for accurate statistical extraction of electrical parameters of High Electron Mobility Transistor (HEMT) devices for GaN technology. Relevant electrical parameters such as oxide capacitance, threshold voltage, effective mobilities and access resistance are extracted. This protocol has been verified over a large range of channel lengths for two normally-off device HEMT GaN wafers having different levels of access resistances.

In SiN/AlGaN/GaN heterostructures, the evaluation of interface charges at the SiN/AlGaN and AlGaN/GaN interfaces is crucial since they both rule the formation of the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface. In this paper, we conducted a thorough analysis of the gate-to-channel capacitance CGC(VG) and of the drain current ID(VG) over a gate voltage VG range enabling the depletion of the 2DEG and the formation of the electron channel at the SiN/AlGaN interface. This work includes the establishment of analytical equations for VTH1 (formation of the 2DEG) and VTH2 (formation of the electron channel at the SiN/AlGaN interface) as a function of interface charges and of the p-doping below the 2DEG. The inclusion of the p-doped layer below the 2DEG and the use we made of VTH2 have not been reported in previous studies. Our analysis allows a reliable estimate of the interface charges at the AlxGa1−xN/GaN and SiN/AlxGa1−xN interfaces for various Al concentrations x as well as to demonstrate that the polarization charge at the SiN/AlxGa1−xN interface is compensated, which confirms previous findings. Moreover, this compensation is found to be induced by the AlGaN layer rather than the SiN layer.

In this article, threshold-voltage V TH instabilities under positive gate voltage stress V GStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast V G ramp was applied in this study. PBTI transients performed at different V GStress and several temperatures highlight the influence of two trap populations, one being related to Al 2 O 3 gate oxide defects and the other one to C N acceptors in GaN lattice. Both trap populations are located close to the Al 2 O 3 /GaN interface and lead to V TH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8-0.9 eV related to C N traps and an energy range between 0.7 and 1.5 eV ascribed to Al 2 O 3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the totalmetal-insulatorsemiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and themain flat part of the channel HEMTs. Second, the differential method allows the split- CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al2O3/UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.

In this paper, threshold voltage VTH instabilities under positive gate voltage stress (VGStress) are thoroughly investigated on GaN-on-Si Enhancement-mode MOS-channel HEMTs. An analysis of pBTI transients performed at several VGStress and temperatures (T) reveals two trap populations close to the Al2O3/GaN interface namely (1) CN acceptors in the GaN substrate, and (2) defects in the Al2O3 gate oxide. Both trap populations lead to VTH instabilities via different underlying mechanisms as evidenced by TCAD simulations. At VGStress < 1.5 V, VTH drifts are ascribed to CN traps ionization localized at 0.8-0.9eV above the valence band (Ev). At higher VGstress, electron trapping also occurs in Al2O3 defects leading to stronger VTH degradation. DC & AC pBTI transients have been modeled using Capture Emission Time (CET) map approach, which allowed the identification of both trap populations. Temperature-dependent CET maps extraction reveals a strong activation of CN traps with temperature, and confirms Arrhenius analysis consistency. This study provides a deep understanding of BTI reliability in GaN-HEMT technologies.

In lateral power diodes, the conductivity modulation mechanism can pave the way to the demonstration of surge current capability. In a Hybrid Anode Diode concept with a p-GaN layer, an anode contact on p-GaN layer can be a source of hole injection that increases the electron density at AlGaN/GaN interface. The role of p-GaN layer on the surge current capability and its demonstration are investigated through TCAD simulations that explain the role of hole barrier tunneling at anode metal/p-GaN interface. These simulations show that surge current can occur in case of Ohmic p-GaN contact as the injected holes can lead to create additional electron density in the channel as well as a hole current to support the total diode current.