This paper presents the recent mmWave and sub-THz oriented technology developments as part of RF design-technology co-optimization (DTCO) efforts in Intel 22nm FinFET process (22FFL). Several back-end-of-line (BEOL) and front-end-of-line (FEOL) improvements have been implemented for high frequency applications. In the newly developed BEOL, ExpressVia is introduced, which allows direct transistor connection to thick metal. Continuous via and 3+1 thick metal layers are enabled for design flexibility. The high performance RF transistor (RF HP) is optimized with the new BEOL and characterized at top metal. Additional process improvements in high power RF device (HyPowerFF) and varactors are also implemented. These BEOL and FEOL improvements enable high performance, innovative mmWave and sub-THz circuits and systems.

This work illustrates the use of device-physics and system-level understanding to demonstrate a novel device-technique to achieve high-linearity in RF-GaN HEMTs. By eliminating access-regions and engineering device-transfer function (gm and its derivatives), a significant boost in large-signal non-linearity: 20 dB reduction in harmonics, OIP3 boost by 6 dB is shown. The full potential of this technique in providing IMD below the state-of-art is highlighted in commercial RF-devices using physical-MVSG model.

Gallium nitride (GaN) high-electron mobility transistors (HEMTs) are a key technology for realizing next generation high-power RF amplifiers and high-efficiency power converters. However, elevated channel temperatures due to self-heating often severely limit their power handling capability. Although the steady-state thermal behavior of GaN HEMTs has been studied extensively, significantly fewer studies have considered their transient thermal response. In this paper, we report a methodology for measuring the transient temperature rise and thermal time constant spectrum of GaN HEMTs via time-resolved micro-Raman thermometry with a temporal resolution of 30 ns. We measured a broad spectrum of time constants from approximate to 130 ns to approximate to 3.2 ms that contribute to the temperature rise of an ungated GaN-on-SiC HEMT due to aggressive, multidimensional heat spreading in the die and die-attach. Our findings confirm previous theoretical analysis showing that one or two thermal time constants cannot adequately describe the transient temperature rise and that the temperature reaches steady-state at approximate to 16L(2)/pi(2)alpha, where L and alpha are the thickness and thermal diffusivity of the substrate. This paper provides a practical methodology for validating transient thermal models of GaN HEMTs and for obtaining experimental values of the thermal resistances and capacitances for compact electrothermal modeling.

Obtaining a subthreshold swing (SS) below the thermionic limit of 60 mV dec(-1) by exploiting the negative-capacitance (NC) effect in ferroelectric (FE) materials is a novel effective technique to allow the reduction of the supply voltage and power consumption in field effect transistors (FETs). At the same time, two-dimensional layered semiconductors, such as molybdenum disulfide (MoS2), have been shown to be promising candidates to replace silicon MOSFETs in sub-5 nm-channel technology nodes. In this paper, we demonstrate NC MoS2 FETs by incorporating a ferroelectric Al-doped HfO2 (Al: HfO2), a technologically compatible material, in the FET gate stack. Al : HfO2 thin films were deposited on Si wafers by atomic layer deposition. Voltage amplification up to 1.25 times was observed in a FE bilayer stack of Al : HfO2/HfO2 with a Ni metallic intermediate layer. The minimum SS (SSmin) of the NC-MoS2 FET built on the FE bilayer improved to 57 mV dec(-1) at room temperature, compared with SSmin (=) 67 mV dec(-1) for the MoS2 FET with only HfO2 as a gate dielectric.

Gallium Nitride (GaN) and other III-N semiconductors are rapidly gaining importance in high power and high frequency electronic applications. III-N material based devices are fabricated on heterostructures that are usually grown by high vacuum techniques such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). However, in many applications, it is necessary to regrow thin cap layers of III-N materials during device fabrication. One such application is regrowth of ohmic contacts to III-N devices. Heavily doped n+ GaN, or InGaN grown by MBE or MOCVD is used to obtain low resistance non-alloyed ohmic contacts to GaN based devices. However, from a commercial point of view, this becomes difficult because of the high cost and lack of availability of ultra high vacuum (~1x10-10 Torr) techniques in most clean room facilities. Reactive sputtering provides a cheaper and more ubiquitous alternative for the growth of thin cap layers on parent MOCVD III-N heterostructures during device fabrication. In this work, we explore the possibility of using reactive sputtering as a method to grow III-N materials as ohmic contacts to GaN based devices.

Mechanical stress is an important factor influencing the performance and reliability of GaN-based devices. In highly piezoelectric materials like AlGaN/GaN, mechanical stress directly influences the piezoelectric polarization, and hence the charge density of the 2-D electron gas. Fabrication processes for devices as well as device operating conditions can change the mechanical stress in AlGaN/GaN transistors. In this paper, the mechanical stress resulting from fabrication and operation of AlGaN/GaN transistors has been modeled using a finite element analysis approach. Specifically, the stress induced in AlGaN/GaN by chemical vapor deposition of silicon nitride films is discussed. Furthermore, the temperature-induced mechanical stress during on-state device operation is computed and the effect of source field plates and substrate materials has been investigated. Finally, the above-mentioned stress components are compared with those due to lattice mismatch, epi growth, and inverse piezoelectric effect. The potential impact of mechanical stress on device reliability is also discussed.

Passivation films are used in III-nitride (III-N) based devices to suppress current collapse and improve frequency performance. Several passivation films and deposition methods have the added effects of increasing the dc ON- and OFF-state currents in devices. In this paper, the physical mechanisms behind this current increase have been studied in both nanoribbon and planar devices with atomic-layer deposited Al 2 O 3 passivation. Increased tensile stress in the AlGaN layer due to passivation leads to an increase in the charge density in nanoribbon devices. Simultaneously, the mobility in nanoribbons increases after Al 2 O 3 passivation. These effects lead to a large (~118%) increase in the saturation drain current in nanoribbon devices. In contrast, fixed positive charge at the Al 2 O 3 -AlGaN interface leads to a small (~6%) saturation drain current increase in planar devices. In addition, the mechanisms behind the increase in the OFF-state drain current in the passivated devices are investigated. Schottky barrier lowering and the increase in surface and buffer conduction are found to be the major causes for the OFF-state current increase with passivation.

Ohmic contacts fabricated by regrowth of n(+) GaN are favorable alternatives to metal-stack-based alloyed contacts in GaN-based high electron mobility transistors. In this paper, the influence of reactive ion dry etching prior to regrowth on the contact resistance in AlGaN/GaN devices is discussed. We demonstrate that the dry etch conditions modify the surface band bending, dangling bond density, and the sidewall depletion width, which influences the contact resistance of regrown contacts. The impact of chemical surface treatments performed prior to regrowth is also investigated. The sensitivity of the contact resistance to the surface treatments is found to depend upon the dangling bond density of the sidewall facets exposed after dry etching. A theoretical model has been developed in order to explain the observed trends. Published by AIP Publishing.

Variable-range-hopping through dislocations was identified as the main off-state leakage mechanism for GaN vertical diodes on different substrates. The behavior of leakage current for vertical devices as a function of dislocation density and electric field was derived by TCAD simulations, after careful calibration with experiments and literature data. Designed GaN vertical diodes demonstrate 2-4 orders of magnitude lower leakage current while supporting 3-5 times higher electric field, compared to GaN lateral, Si and SiC devices.

Positron annihilation is a non-destructive tool for investigating vacancy-type defects in materials. Detectable defects are monovacancies to vacancy clusters, and there is no restriction onsample temperature or conductivity. Using this technique, we studied native and plasma-treatment induced defects in GaN layers grown on Si substrates deposited by metal organic chemical vapor deposition. Measurements of Doppler broadening spectra of the annihilation radiation for 1-μm-thick GaN layers showed that optically active vacancy-type defects were formed during their growth. These defects were identified as complexes of vacancies and carbon impurities. For plasma treated samples, we found the introduction of vacancy-type defects in the subsurface region (≤2.5 nm). These results show that positron annihilation spectroscopy is a useful tool for identifying vacancy-type defects in GaN-based devices.

A BCl3 surface plasma treatment technique to reduce the resistance and to increase the uniformity of ohmic contacts in AlGaN/GaN high electron mobility transistors with a GaN cap layer has been established. This BCl3 plasma treatment was performed by an inductively coupled plasma reactive ion etching system under conditions that prevented any recess etching. The average contact resistances without plasma treatment, with SiCl4, and with BCl3 plasma treatment were 0.34, 0.41, and 0.17 Ω mm, respectively. Also, the standard deviation of the ohmic contact resistance with BCl3 plasma treatment was decreased. This decrease in the standard deviation of contact resistance can be explained by analyzing the surface condition of GaN with x-ray photoelectron spectroscopy and positron annihilation spectroscopy. We found that the proposed BCl3 plasma treatment technique can not only remove surface oxide but also introduce surface donor states that contribute to lower the ohmic contact resistance.

This thesis is divided in two parts. First, self-consistent electro-thermal simulations have been performed for single finger and multi-finger GaN-based vertical and lateral power transistors and were validated with experimental DC characteristics. The models were used to study the thermal performance of GaN-based vertical metal oxide semiconductor field-effect transistors (MOSFETs) and the lateral high electron mobility transistors (HEMTs) designed for different breakdown voltage application and at different size scaling levels. The comparison between two structures revealed that the vertical MOSFETs have the potential to achieve an up to 50% higher thermal performance, especially for higher breakdown voltage and higher size scaling level designs. Second, normally-off lateral MOS-HEMTs were developed by the combination of fluorine plasma treatment and high-temperature gate oxide deposition. Record performances have been achieved for the fluorinated MOS-HEMTs with a threshold voltage >3.5 V, a low on-resistance ~ 2 mΩ·cm 2 , a small threshold voltage hysteresis ~0.15 V, high enhancement-mode channel mobility ~ 1000 cm 2 V -1 s -1 , a breakdown voltage ~ 780 V, no current collapse and a stability with 24 h continuous on-state operation at 250 o C. In addition, an analytical model for the threshold voltage of fluorinated MOS-HEMTs was established for the first time, to enable accurate design and engineering of the threshold voltage for MOS-HEMTs. This novel technology has been demonstrated as promising to fabricate high-performance normally-off MOS-HEMTs.

AlGaN/GaN high-electron-mobility transistors (HEMTs) have great potential for the next generation of power electronics. In this application, enhancement-mode (E-mode) metal-oxide-semiconductor (MOS) HEMTs with a threshold voltage (Vth) ~ 3 V are highly desirable as they allow simpler circuits and fail-safe operation. However, it has been recently shown that the Vth in GaN MOS-HEMT structures does not typically increase by increasing the gate oxide thickness, due to the presence of positive interface charges and oxide bulk charges [1]. On the other hand, a high Vth was reported in fluorinated MOS-HEMTs (~5 V) [2], although no analysis or explanation have been presented for this behavior. There is, therefore, a need for a systematic study of the Vth in fluorinated MOS-HEMTs. In this work, E-mode fluorinated MOS-HEMTs were realized with a Vth higher than 3 V and a Vth increasing with the gate oxide thickness and fluorine plasma time. A comprehensive analytical model for Vth was proposed for fluorinated MOS-HEMTs for the first time and was verified by experimental data. Moreover, fluoride-induced negative bulk charge inside the oxide layer was demonstrated to significantly contribute to the high Vth. This suggests that the fluorine plasma treatment is a promising technique to facilitate a high Vth for E-mode MOS-HEMTs.

This paper demonstrates the compensation of the intrinsic positive charges in Al2O3 gate dielectric by fluorine ions in GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs). Negatively-charged fluorine ions diffused into the oxide from the AlGaN barrier during the 250 °C atomic layer deposition compensate the intrinsic positive charge present in the Al2O3. This compensation is key to control the threshold voltage (Vth) of enhancement-mode (E-mode) transistors. A comprehensive analytical model for the Vth of fluorinated MOS-HEMTs was established and verified by experimental data. This model allows the calculation of the different charge components in order to optimize the transistor structure for E-mode operation. Using the proposed charge compensation, the Vth increases with gate dielectric thickness, exceeding 3.5 V for gate dielectrics 25 nm thick.