Analog blocks intended for software defined radio have to be targeted to multi-standard operation trying to guarantee at any time a near optimal power-performance trade-off. A novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) is here defined. These baseband blocks are driven by a network-on-chip that is able to set performances like cut-off frequency, selectivity, noise, and gain conveniently adapting the power consumption. The LPF provides a wide frequency tuning range between 0.35MHz and 23.5MHz with an adaptive integrated noise level between 85muVrms and 163muVrms and a current consumption that moves from 1.5mA to 18mA. The VGA is made up of 2 cascaded gain stages and provides a gain range from 0dB to 39dB. The prototype was realized in 0.13mum CMOS technology. Measurements results validate the adopted approach

The 4th generation of wireless systems needs low-power integrated transceivers that can be reconfigured in order to satisfy different standard requirements. Standard analog blocks are often not suitable for this step towards the future because of their lack of flexibility. We defined a novel approach to make active-Gm-RC biquadratic cells completely reconfigurable. The biquad provides digitally programmable bandwidth and hence power consumption with a fully customizable cut-off frequencies range. Besides, the noise level can be conveniently modified leading to a further power saving. We exemplified the use of this basic building block in the design of a flexible low-pass filter for a zero-IF transceiver. A 2nd/4th/6th order Butterworth filter was implemented with a continuous cut-off frequency tuning between 330 KHz and 24.6 MHz and with a current consumption range between 0.6mA to 26mA

An efficient substrate-noise-reduction technique for synchronous CMOS circuits shows >2/spl times/ noise reduction with penalties of 3% area and 4% power increase in a 5k-gate synchronous CMOS circuit fabricated in a 0.35 /spl mu/m CMOS process on an epi-type substrate.

Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends.

Introduction Substrate Noise Generation. low-level (SPICE) modeling and measurements. Conclusions IMEC 2000generationpropagationimpactGoal: simulate substrate noisegeneration of large digital circuits IMEC 2000Approach:. Find simple but accurate SPICE substrate modelsfor digital standard cells. Very the SPICE substrate noise simulations withmeasurements. Develop a high-level substrate noise simulationmethodology, based on the SPICE models. At first, for low-ohmic...

A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 μm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement

In mixed-signal ASICs coupling from switching digital nodes and from the digital power supply to analog circuits via the common substrate can degrade the performance of the analog circuits. This paper describes a design experiment to measure the time domain behavior and spectral content of such substrate coupling noise. To measure this noise over a wide frequency range a novel analog substrate noise sensor has been designed. Using this sensor, substrate noise has been measured in the time and frequency domain. Also the influence of supply voltage, switching activity and mounting technique on the substrate noise are experimentally investigated. Simulation results, using a SPICE substrate model, are also included. The presented measurements show that careful investigation of the spectral content of substrate noise is important in the design of mixed-signal ASICs. Differences between the peak noise levels and the noise floor can easily be 40 dB

Substrate coupling in mixed-signal ASICs can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation and impact of substrate noise. Recent studies have mainly concentrated on the time domain behavior of generated substrate noise and dealt mostly with noise injection from a single noise source. This paper will focus on the generation of substrate noise by digital circuits and on the spectral content of this noise. To simulate the noise generation a SPICE substrate model has been developed, which allows accurate simulation of substrate noise generated by small digital circuits. The correctness of this model has been verified with measurements of substrate noise on a test chip, using a novel wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. It is shown that the difference between spectral noise peaks and the noise floor can be up to 40 dB.