Parallelized DNA synthesis across a dense array of sites is crucial to high-throughput synthetic biology and diagnostics and could potentially be used for DNA-based data storage. Phosphoramidite synthesis can achieve substantial parallelism but relies on harmful solvents and centralized facilities. Enzymatic DNA synthesis in mild aqueous solution is safer and could be more accessible, but parallel demonstrations remain modest at an early stage. Here we show that a complementary metal-oxide-semiconductor chip can be used to perform parallel enzymatic DNA synthesis of up to 64 distinct 38-39-nucleotide sequences (10-11-nucleotide feature sequences). The chip controls an array of 256 ring-electrode pairs (each one a programmable synthesis site) that can create an arbitrary pattern of localized acidity to enable DNA deprotection and subsequent enzymatic nucleotide incorporation. We also illustrate the potential of this parallel synthesis for data storage by encoding a 169-byte text. Our mechanistic analysis shows that shifting from an indirect to a direct local-acid chemistry route could lead to higher-throughput enzymatic synthesis that can scale with the complementary metal-oxide-semiconductor chip.

– Intracellular recording offers exquisite access to the electrical interior of a neuron––detecting not only spikes but also the small synaptic signals that reflect synaptic connections and their properties––but it had been limited to only one cell at a time. In 2020, a CMOS nanoelectrode array broke this constraint and massively parallelized intracellular recording, opening a path to capturing synaptic signals across a neuronal network. This shift led us in 2021 to propose thecopyframework: population-scale intracellular recording is a process of copying a biological network, because the resulting data––rich with synaptic signals from across the network––reveal its synaptic connectivity map. In this Perspective, we revisit that framework because the recent CMOS intracellular microelectrode array (iMEA), building on the 2020 nanoelectrode array, transforms copy from a demanding demonstration into a practical, high-yield technology. By routinely recording intracellular signals across thousands of neurons, the iMEA uncovers synaptic organization with a breadth and clarity previously unreachable. We outline the development of the iMEA as an improved copy platform, what it now enables, and what must still be advanced to build a richer synaptic connectivity map––one that is indispensable to understanding how the brain functions, and provides a firmer foundation for neuromorphic models grounded in the brain’s own wiring.

The demand for high-throughput, multi-modal recording and stimulation in neuroscience research has driven the development of neural interfaces that optimize area and energy efficiency without compromising noise performance. Simultaneously, the need for on-chip data compression to reduce data volume has become increasingly critical. This work presents a neural interface system-on-chip (NISoC) that incorporates 1,024 channels for simultaneous electrical recording and stimulation, enabling high-resolution, high-throughput electrophysiology with record noise-energy efficiency. The 2 mm $\boldsymbol{\times}$ 2 mm NISoC, fabricated using 65 nm CMOS technology, integrates a 32 $\boldsymbol{\times}$ 32 array of electrodes vertically coupled to analog front-ends. These front-ends support both voltage and current clamping through a programmable interface, providing a voltage range up to 100 dB and a current range of 120 dB. Each channel operates at a power consumption of 0.81 $\mu$W, achieving an input-referred voltage noise of 8.8 $\mu V_{rms}$ over a signal bandwidth from DC to 12.5 kHz. The NISoC also integrates on-chip data acquisition through a back-end array of 32 dynamic incremental SAR ADCs, achieving 25 Msps and 11 effective number of bits (ENOB) acquisition with an energy efficiency of 2 fJ/level. The dynamic incremental SAR ADC architecture further offers additional functionality of intrinsic spike detection for future on-chip neural data compression.

The massive parallelization of neuronal intracellular recording, which enables the measurement of synaptic signals across a neuronal network, and thus the mapping and characterization of synaptic connections, is an open challenge, with the state of the art being limited to the mapping of about 300 synaptic connections. Here we report a 4,096 platinum/platinum-black microhole electrode array fabricated on a complementary metal-oxide semiconductor chip for parallel intracellular recording and thus for synaptic-connectivity mapping. The microhole-neuron interface, together with current-clamp electronics in the underlying semiconductor chip, allowed a 90% average intracellular coupling rate in rat neuronal cultures, generating network-wide intracellular-recording data with abundant synaptic signals. From these data, we extracted more than 70,000 plausible synaptic connections among more than 2,000 neurons and catalogued them into electrical synaptic connections and into inhibitory, weak/uneventful excitatory and strong/eventful excitatory chemical synaptic connections, with an estimated overall error rate of about 5%. This scale of synaptic-connectivity mapping and the ability to characterize synaptic connections is a step towards the functional connectivity mapping of large-scale neuronal networks.

We introduce a bioelectronic interface between biological electrogenic cells and a mixed-signal CMOS integrated circuit with an array of surface electrodes, where not only is the CMOS electrode array capable of electrophysiological recording and stimulation of the cells with 1,024 recording and stimulation channels, but it can also provide low-latency artificial signal pathways from cells it records to cells it stimulates. This on-chip closed-loop modulation has an intrinsic latency less than 5 µs. To demonstrate the utility of the on-chip closed loop modulation as an artificial feedback pathway between biological cells, we develop a silicon-cardiomyocyte self-sustained oscillator with a tunable frequency to which both the relevant part of the CMOS chip and cells are locked, and also a silicon-neuron interface with a silicon inhibitory connection between neuronal cells. This line of cyto-silicon hybrid system, where the boundary between biological and semiconductor systems is blurred, may find applications in prosthesis, brain-machine interface, and fundamental biology research.

Intracellular electrophysiology, a vital and versatile technique in cellular neuroscience, is typically conducted using the patch-clamp method. Despite its effectiveness, this method poses challenges due to its complexity and low throughput. The pursuit of multi-channel parallel neural intracellular recording has been a long-standing goal, yet achieving reliable and consistent scaling has been elusive because of several technological barriers. In this work, we introduce a micropower integrated circuit, optimized for scalable, high-throughput in vitro intrinsically intracellular electrophysiology. This system is capable of simultaneous recording and stimulation, implementing all essential functions such as signal amplification, acquisition, and control, with a direct interface to electrodes integrated on the chip. The electrophysiology system-on-chip (eSoC), fabricated in 180nm CMOS, measures 2.236 mm × 2.236 mm. It contains four 8 × 8 arrays of nanowire electrodes, each with a 50 μm pitch, placed over the top-metal layer on the chip surface, totaling 256 channels. Each channel has a power consumption of 0.47 μW, suitable for current stimulation and voltage recording, and covers 80 dB adjustable range at a sampling rate of 25 kHz. Experimental recordings with the eSoC from cultured neurons in vitro validate its functionality in accurately resolving chemically induced multi-unit intracellular electrical activity.

We report a mixed-signal CMOS chip with an array of surface electrodes, which is capable of not only electrophysiological recording and stimulation of biological cells but also low-latency closed-loop modulation between the recorded and stimulated cells. To demonstrate the utility of the on-chip closed-loop modulation as an artificial feedback pathway between biological cells, we have developed a silicon-cardiomyocyte self-sustained oscillator with a tunable locked frequency and a silicon-neuron interface that offers an artificial (silicon) inhibitory connection between neurons. These chip-cell interfaces smear the boundary between biological and semiconductor systems.

Neuromorphic engineering aims at designing and building electronic systems that emulate the function and organization of nervous systems in very large-scale integration (VLSI) technology. Current neuromorphic VLSI hardware can now emulate large-scale neural network models with up to a million of silicon neurons, as well as various computational primitives involved in pattern recognition, learning, classification, and decision-making processes. These advances have spurred the development of closed-loop biohybrid circuits between populations of biological neurons and neural networks of silicon neurons. Biohybrid systems provide biological realism and relevance for investigating neuronal network functions and for fast prototyping of bidirectional neuromorphic neural interfaces and neuroprosthetic devices. This chapter describes the current efforts toward large-scale neuromorphic neural interfaces and their emerging applications in closed-loop neuroscience, for the study of neuronal networks at multiple timescales and levels of biological organization, and in neuroprosthetics, for the restoration of sensory, motor, and cognitive functions.

This article presents the design of an area/ power-efficient discrete-time (DT) delta-sigma ( $\Delta \Sigma $ ) modulator suitable for multichannel sensor applications. First, the area efficiency of the modulator is achieved by optimizing the size of the sampling capacitor with the compact integrators based on the dynamic-boost inverter (DBI). The DBI is designed to have a small active area of only 0.00044 mm2, due to its self-bias scheme that eliminates the need for additional hardware for biasing circuitry. Second, the power efficiency is improved through the quantitative design approach to reduce the power consumption of the integrators by optimizing the gain–bandwidth product (GBW) of the DBI-based OTA in each integrator. In addition, the static current consumption of the integrators is further reduced due to the power-saving feature of the DBI utilizing the principle of a composite transistor. Finally, the self-bias scheme ensures that the DBI maintains a dc gain of 44.3 dB despite circuit mismatch by balancing the currents of the nMOS and pMOS transistors in the DBI. The prototype modulator, fabricated using 0.18- $\mu \text{m}$ CMOS technology, occupies an active area of 0.0939 mm2. For a 25-kHz bandwidth (BW), the modulator achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB with a power supply rejection ratio (PSRR) of 56.8 dB and a common-mode rejection ratio (CMRR) of 66.1 dB at a 1.8-V supply. The modulator also maintains an SNDR higher than 82.5 dB and a DR higher than 85.5 dB for a 5–25-kHz BW with an ${\mathrm {FoM}}_{W}$ of 78.4–103.4 fJ/conversion at a 1.5–1.8-V supply.

Aqueous Ionic Circuits An ionic circuit developed by Woo-Bin Jung, Donhee Ham, and co-workers in article number 2205096 computes in water. It can execute a core of neural-net computing in an analog manner fully based on electrochemical principles in an aqueous solution of quinone. This ionic circuit thus demonstrates a step toward sophisticated aqueous ionics.

Using ions in aqueous milieu for signal processing, like in biological circuits, may potentially lead to a bioinspired information processing platform. Studies, however, have focused on individual ionic diodes and transistors rather than circuits comprising many such devices. Here a 16 × 16 array of new ionic transistors is developed in an aqueous quinone solution. Each transistor features a concentric ring electrode pair with a disk electrode at the center. The electrochemistry of these electrodes in the solution provides the basis for the transistor operation. The ring pair electrochemically tunes the local electrolytic concentration to modulate the disk's Faradaic reaction rate. Thus, the disk current as a Faradaic reaction to the disk voltage is gated by the ring pair. The 16 × 16 array of these transistors performs analog multiply-accumulate (MAC) operations, a computing modality hotly pursued for low-power artificial neural networks. This exploits the transistor's operating regime where the disk current is a multiplication of the disk voltage and a weight parameter tuned by the ring pair gating. Such disk currents from multiple transistors are summated in a global reference electrode to complete a MAC task. This ionic circuit demonstrating analog computing is a step toward sophisticated aqueous ionics.

Amplifiers in biomedical sensing systems play a crucial role in elucidating often weak biosignals such as those originating from the brain in electroencephalograms (EEG) but can suffer from flicker (1/f) and thermal noise. Correlated double-sampling (CDS) is a method that can be used to reduce low frequency noise. Conventionally implemented as an analog reset of the amplifier between samples of interest, the CDS operation adds kT/C sampling noise which may exceed the low-frequency noise being removed, especially if the reset is not allowed adequate time to settle. Analog CDS therefore, puts a limitation on the sampling frequency of such sensing systems, making them less ideal for the fast, high-bandwidth acquisition required for applications such as neural interfaces. Digital CDS is presented here as a technique which relies on intermittent sampling of an internal reference voltage taken during brief disconnections from the sensor between real samples for a noise correction performed digitally post-acquisition. This work demonstrates the implementation of digital CDS on a neural interface system-on-chip (NISoC) and details the optimization of a windowed weighting correction algorithm to achieve a 71% improvement in noise performance. In-Ear EEG and EOG recordings were performed with and without CDS for comparison.

pH controls a large repertoire of chemical and biochemical processes in water. Densely arrayed pH microenvironments would parallelize these processes, enabling their high-throughput studies and applications. However, pH localization, let alone its arrayed realization, remains challenging because of fast diffusion of protons in water. Here, we demonstrate arrayed localizations of picoliter-scale aqueous acids, using a 256-electrochemical cell array defined on and operated by a complementary metal oxide semiconductor (CMOS)–integrated circuit. Each cell, comprising a concentric pair of cathode and anode with their current injections controlled with a sub-nanoampere resolution by the CMOS electronics, creates a local pH environment, or a pH “voxel,” via confined electrochemistry. The system also monitors the spatiotemporal pH profile across the array in real time for precision pH control. We highlight the utility of this CMOS pH localizer-imager for high-throughput tasks by parallelizing pH-gated molecular state encoding and pH-regulated enzymatic DNA elongation at any selected set of cells.

We present a neural interface system-on-chip (NISoC) with 1,024 channels of simultaneous electrical recording and stimulation for high-resolution high-throughput electrophysiology. The 2mm × 2mm NISoC in 65nm CMOS integrates a 32 × 32 array of electrodes vertically coupled to analog front-ends supporting both voltage and current clamping through a programmable interface, ranging over 100dB in voltage and 120dB in current, with 0.82μW power per channel at 5.96μV rms input-referred voltage noise from DC to 12.5kHz signal bandwidth. This includes on-chip acquisition with a back-end array of 32 dynamic incremental SAR ADCs for 25Msps 11-ENOB acquisition at 2fJ/level FOM.

Nanoscale multipoint structure-function analysis is essential for deciphering the complexity of multiscale biological and physical systems. Atomic force microscopy (AFM) allows nanoscale structure-function imaging in various operating environments and can be integrated seamlessly with disparate probe-based sensing and manipulation technologies. Conventional AFMs only permit sequential single-point analysis; widespread adoption of array AFMs for simultaneous multipoint study is challenging owing to the intrinsic limitations of existing technological approaches. Here, we describe a prototype dispersive optics-based array AFM capable of simultaneously monitoring multiple probe-sample interactions. A single supercontinuum laser beam is utilized to spatially and spectrally map multiple cantilevers, to isolate and record beam deflection from individual cantilevers using distinct wavelength selection. This design provides a remarkably simplified yet effective solution to overcome the optical cross-talk while maintaining subnanometer sensitivity and compatibility with probe-based sensors. We demonstrate the versatility and robustness of our system on parallel multiparametric imaging at multiscale levels ranging from surface morphology to hydrophobicity and electric potential mapping in both air and liquid, mechanical wave propagation in polymeric films, and the dynamics of living cells. This multiparametric, multiscale approach provides opportunities for studying the emergent properties of atomic-scale mechanical and physicochemical interactions in a wide range of physical and biological networks.

Objective: Although biological synapses express a large variety of receptors in neuronal membranes, the current hardware implementation of neuromorphic synapses often rely on simple models ignoring the heterogeneity of synaptic transmission. Our objective is to emulate different types of synapses with distinct properties. Methods: Conductance-based chemical and electrical synapses were implemented between silicon neurons on a fully programmable and reconfigurable, biophysically realistic neuromorphic VLSI chip. Different synaptic properties were achieved by configuring on-chip digital parameters for the conductances, reversal potentials, and voltage dependence of the channel kinetics. The measured I-V characteristics of the artificial synapses were compared with biological data. Results: We reproduced the response properties of five different types of chemical synapses, including both excitatory ($AMPA$, $NMDA$) and inhibitory ($GABA_A$, $GABA_C$, $glycine$) ionotropic receptors. In addition, electrical synapses were implemented in a small network of four silicon neurons. Conclusion: Our work extends the repertoire of synapse types between silicon neurons, providing greater flexibility for the design and implementation of biologically realistic neural networks on neuromorphic chips. Significance: A higher synaptic heterogeneity in neuromorphic chips is relevant for the hardware implementation of energy-efficient population codes as well as for dynamic clamp applications where neural models are implemented in neuromorphic VLSI hardware.

High-density multi-channel neural recording is critical to driving advances in neuroscience and neuroengineering through increasing the spatial resolution and dynamic range of brain-machine interfaces. Neural-signal-acquisition ICs have conventionally been designed composed of two distinct functional blocks per recording channel: a low-noise amplifier front-end (AFE), and an analog-digital converter (ADC) [1,2]. Hybrid architectures utilizing oversampling ADCs with digital feedback [3-5] have seen recent adoption due to their increased power and area efficiency. Still, input dynamic range (DR) is relatively limited due to aggressive supply voltage scaling and/or kT/C sampling noise. This paper presents a neural-recording ADC chip with 92dB input dynamic range and 0.99μV rms of noise at 0.8μW power consumption per channel over 500Hz signal bandwidth, owing to 1) a predictive digital autoranging (PDA) scheme in a hybrid analog-digital 2 nd -order oversampling ADC architecture, 2) no specific sampling process through capacitors, avoiding kT/C noise altogether. Digitally predicting the analog input at 12b resolution from a 1b quantization of the continuously integrated residue at effective 32 oversampling ratio (OSR), the PDA handles a ±130mV electrode differential offset (EDO) and recovers from >200mV pp transient artifacts within <1ms. Furthermore, using digital circuits for integration ensures the architecture benefits from process scaling and the resulting compactness makes it suitable for incorporation in high-density recording arrays.