Traditional 2-D SRAM scaling has been slowing down and suffers from high parasitic resistance of critical signals like wordline (WL) and bitline (BL). As 3-D technologies such as hybrid wafer bonding (HWB) mature, increasingly finer pitches of 3-D interconnects are possible, enabling the possibility of 3-D partitioned memory designs. 3-D-split SRAMs, realized by splitting or folding an SRAM macro across two or more die stacks, may reduce the delay and power incurred inside the macro by mitigating the BL or WL signal RC parasitics. However, the efficacy of such a 3-D-split SRAM would depend on the parasitic overhead of the inter-tier 3-D back-end-of-line (3-D-BEOL) interconnects. We perform an early exploration of the BEOL options in the context of HWB and propose two separate approaches for optimizing the BEOL for 3-D-split SRAM designs. Measured results from 12 nm FinFET 64 kb prototype SRAM macros, designed in 2-D, but configured to capture the parasitic effects of 3-D-BEOL interconnects, indicate that 3-D-split SRAMs can provide 110–127 mV lower ${V} _{\text {MIN}}$ or 9%–14% faster access time, equivalent to the gains achieved with one full process node dimensional scaling.

This work demonstrates face-to-face hybrid wafer bonding at GLOBALFOUNDRIES, including fine pitch characterization and processing, along with preliminary reliability results. Bonding alignment data analysis is shown, as it is imperative to have high bonding alignment in order to assure full yield of the fine pitch interconnects. As a preliminary proof-of-concept check, simple device test data is shown as a way to electrically analyze the bond quality. Limited thermal stress testing results for reliability (utilizing JEDEC-type standards) are shown as well, proving a robust build quality.

The impact of wafer level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) reliability. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) behavior indicates that there is negligible impact on Idsat due to mechanical stress of the TSV for 5 μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed at 25°C and 125°C to study the FEOL gate dielectric and device reliability such as gate dielectric breakdown voltage (VBD), Hot Carrier Injection (HCI), and Bias Temperature Instability (BTI). Apart from FEOL reliability study, special test structures were also designed to capture even a minor TSV impact on the lower metal and via levels of the BEOL stack. Time Dependent Dielectric Breakdown (TDDB), Electro migration (EM), and Stress Migration (SM) were performed to investigate any potential impact to BEOL due to TSV mechanical stress or Cu pumping effects. TSV KOZ impact on electrostatic discharge (ESD) protection devices was also performed. Our study with thick and thin TSV wafer showed no significant impact of TSV integration approach on FEOL, BEOL and ESD reliability.

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

The integration of Through-Silicon Vias (TSVs) in CMOS wafers has the potential to cause performance shifts of devices in close proximity due to mobility change caused by mechanical stress. To ensure successful integration of TSV into a baseline technology, these shifts must be negligible to allow seamless integration of TSVs into circuit designs. As the first publication of its kind by an advanced node foundry, this paper presents results of a study to analyze TSV impact on 14nm FinFET device and analog circuit performance. These include n or p type short and long channel FETs, current mirrors, and operational amplifiers (op-amp). The unique TSV capture pad structure used by GLOBALFOUNDRIES for advanced node TSV integration is discussed. This structure allows for improved TSV middle integration yield and ensures that a good electrical connection from the back-end of line (BEOL) to the TSV is formed. A physical property analysis was also done on the TSV structure to determine capacitance, leakage, and dielectric liner breakdown voltage. Finally, a full suite of characterization measurements were performed on the 14nm FinFET thin wafers to assess the impact of the wafer thinning process on front-end of line (FEOL) devices.

Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great impact on other downstream processes in TSV module and TSV backside reveal. This paper presents the challenges encountered in developing the 6μm × 55μm TSV (6μm diameter × 55μm depth) with a number of continuous process optimizations. These include improvements to the notch below the hard-mask, an increase in the post-etch resist retention, within wafer depth uniformity and higher silicon etch rate improving the throughput. TSV scaling to 3μm × 50μm with a higher aspect ratio is also demonstrated. This paper also describes details for setup of an Automatic Process Controller (APC) for TSV depth control in a manufacturing environment.

The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for <; 3μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage/Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed to analyze FEOL reliability for degradation phenomena such as Voltage Break Down (VBD), Hot Carrier Injection (HCI), and Bias Temperature stability (BTI). Test structures were designed to investigate TSV impact on the lower metal and via levels of the BEOL stack. BEOL reliability analysis for degradation phenomena such as Time Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Migration (SM) were performed to investigate any potential impact to due to TSV mechanical stress or Cu pumping effects. BEOL Our investigations showed no significant impact to FEOL or BEOL test structures due to the TSV via middle approach.

To date, Plasma Enhanced Chemical Vapor Deposition (PECVD) O3/TEOS has been the prevalent dielectric liner for TSV applications. This process typically results in poor step coverage for high aspect ratio (HAR) TSV scenarios, and also requires a capping layer to provide acceptable reliability performance due to the high moisture content of the O3/TEOS material. This study reports on a high throughput room temperature Atomic Layer Deposition (ALD) batch process for use as a dielectric liner in TSV applications, which provides several advantages over existing processes. Process characterization was completed to achieve a 100nm thickness SiO2 liner for a 6×55μm TSV size with nearly 100% conformal sidewall coverage, demonstrating the usefulness of this process for scaling to 3×50μm TSV size and beyond. Characterization of the ALD SiO2 dielectric liner showed breakdown voltage, leakage, and parasitic capacitance values as good as, or better than, the PECVD O3/TEOS dielectric process of record. In addition, the batch ALD process allows for a significant cost reduction of the overall TSV module. The new ALD SiO2 dielectric liner material was also validated through the downstream TSV fabrication process with no adverse effects.

Cu pumping, or the extrusion of Cu out of a TSV after being subjected to high temperature conditions, is one of the highest risk failure modes to be overcome in the development of TSV-middle integration for 3D packaging technologies. Typical Cu pumping analyses focus on a low number of data points through brute force measurement using cross sectional analysis. The low number of data points gathered for each condition does not provide results with a high statistical confidence level. In addition, it is most likely that the cross section does not provide measurement along the plane that contains the highest amount of Cu pumping, resulting in inaccurate maximum pumping height measurements. In this study, a Cu pumping measurement technique was developed using a production capable scanning white light interferometry (SWLI) system, which enables the collection of hundreds or thousands of individual TSV Cu pumping data points. This enables an accurate statistical comparison between Cu pumping mitigation schemes. Using this technique, multiple TSV plating process and thermal annealing conditions were compared by varying temperature and time to determine the conditions that resulted in the lowest amount of Cu pumping. In addition, an alternate integration scheme was investigated that includes multiple anneal and CMP planarization steps. The experimental results demonstrate that Cu pumping can be kept to a manageable level for high reliability performance.

In the past few years, interest in Through Silicon Via (TSV) processing has grown significantly due to its crucial role in enabling 2.5D and 3D IC advanced packaging integration. TSV quality impacts the electrical performance of the final packaged device. Key TSV process integration and metrology challenges include: (1) Developed critical dimension (DCD), in which the lithography CD of the designed TSV must be measured precisely at a high throughput; (2) Post-etch characterization after via formation (3) After Cu-fill process to monitor for problems such as underfill and voids; (4) Post Chemical-mechanical planarization (CMP) topography due to the large size of the TSV which can impact subsequent layers; (5) Subsequent BEOL processing on a via-middle TSV can induce additional thermal expansion of the TSV upwards into the metal line stack as ‘pumping’. Development of simulated mechanical and thermal stresses of the BEOL for large, inline data collection of pumping reduction experiments is needed to reduce this reliability risk [3]; (6) TSV reveal, in which the backside silicon is removed to expose TSV contacts (Cu) and accurate step height control is required to ensure co-planarity. This paper will discuss the above potential reliability risks and metrology challenges in TSV process development, and will focus on characterization of TSVs at various process steps utilizing Scanning White Light Interferometry (SWLI) metrology, which is a reliable, advanced solution for multiple TSV metrology applications.

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 μm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.

This paper describes the process development of TSV integration with 20nm CMOS technology and device performance characterization for 3D integrated circuit (3DIC) enablement. 6×55um Through-silicon-via (TSV) on 20nm CMOS technology has been developed and demonstrated. Key module process issues, such as V0 high resistance, M1 high leakage and Cu pumping which prevent TSV to be integrated with BEOL through via-middle approach for mobile applications, have been addressed through design of experiments (DOEs) study and process optimization. TSV electrical characterization, TSV's impact on transistor, analog/digital circuits & BEOL performance considering TSV Keep-out-zone (KOZ) & Cu pumping impact have been intensively investigated and presented in this paper. Cu diffusion & contamination during TSV back side integration, i.e. MEOL process, has also been analyzed and monitored with time of flight-secondary ion mass spectrometry (TOF-SIMs) evaluation. Electrical test results confirm that the optimized process is robust and minimizes the impact of TSV KOZ and Cu pumping on device and BEOL interconnects.

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 mu m top entrant critical dimension and 50 mu m depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 mu m TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.

High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron diameter with greater than 12:1 depth to BCD aspect ratio have particularly poor signal to noise ratio in the measured signal. This paper proposes a method for improving the interferometric measurement of these very small and high-aspect ratio TSVs with data showing the feasibility of measuring both BCD and depth of 19:1 aspect ratio TSVs. This work demonstrates the capability to analyze the scanning white-light interferometry (SWLI) signal for such high aspect ratio TSV BCD and depth measurements with >0.95 R2 correlation to reference metrology obtained through cross section SEM. Precision of within 2.5% of nominal BCD and within 0.1% of nominal depth was demonstrated for 10x repeatability measurements.

For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3ppm/°C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this defect is that the bulk micro defect (BMD) in silicon substrate serves as a micro-mask during etching and results in silicon fin defects at TSV bottom. These defects have to be eliminated as they are killer TSV defects for several reasons: (1) could serve as a weak point for isolation liner deposition; (2) could be a weak point for barrier/seed layer deposition; and (3) may cause mechanical failures during TSV backside reveal. Previously, silicon fin defects were removed by switching to a non-BMD silicon substrate for interposer application. However, for TSV integration with FEOL devices, the BMD layer serves as an intrinsic gettering layer for devices, therefore, it cannot be removed from the silicon substrate, which makes it challenging to get rid of silicon fin defects. In order to establish a non-destructive in-line detection method of the fin defects, scanning electron microscope (SEM) automatic process inspection (API) was set up to image the fin defects at the bottom of the trench. A special working point with high depth of focus (DoF) and contrast was created to obtain good top-down SEM imaging of the defects at the bottom of this high-aspect-ratio (HAR) structure. Three types of silicon substrates (A, B, and C) were used for this study to investigate the potential root cause. SEM API results show defect rates of 20%, 3.3% and 0% for substrates A, B, and C, respectively. This is in good agreement with both BMD simulation results and benchmarking data in which substrates A, B, and C had normalized BMD densities of 11.7, 5.74, and 1 cm-3, respectively, with a comparable BMD size of 80~90 nm and a denuded zone (DNZ) depth of 10~15 μm. The correlation between BMD density in a silicon substrate and silicon fin defect rate indicates that BMD is a key root cause for silicon fin defects. To eliminate silicon fin defects, an optimized DRIE process has been developed. On the same type of substrate, the DRIE process with a typical voltage bias results in a defect rate of 6.7%, while no silicon fin defect was detected out of 200 TSVs with a polynomial bias ramp to relatively higher final voltage bias during the last 15 μm etch. The hypothesis is that higher voltage bias is able to sputter away BMD and shows potential to get rid of the silicon fin defects at the TSV bottom. In summary, a capable inspection method, a preferred silicon substrate with BMD spec range, and a promising way for DRIE process optimization to eliminate the silicon fin defect at the TSV bottom have been identified and developed in this work. Detailed results and analysis, particularly the fin defect images, statistical inspection results, BMD benchmarking data, simulation results, and TSV profile with optimized process will be discussed in the paper.

White light interferometry (WLI) has been used in the semiconductor industry for the measurement of topography, step height, and via depth, utilizing its fundamentally short coherence length. This allows the tool to achieve nanometer level resolution, making this technique ideal for through silicon via (TSV) measurements for high aspect ratio vias. In this paper, we will discuss one of the important measurement steps within 20 nm/14 nm technology node TSV processing, and how WLI is applied to make the measurements. For the post-chemical mechanical polish (CMP) dishing measurement near TSV's, we have evaluated a wafer map for processing that includes the wafer center and edge area. The CMP dishing measurement can be broken into two distinct regions of measurement: 1) Within-Field dishing and 2) Within-TSV dishing. Greater than 90% correlation with an AFM measurement for all dishing measurement regions has been observed. Less than 0.5% deviation for repeatability data pertaining to this measurement has also been observed.

A new type of through-silicon via (TSV) defect, silicon fin defect, which was found after the TSV deep-reactive-ion-etching process at the TSV bottom is reported. These defects are considered killer TSV defects that may cause process or mechanical failures and have to be eliminated. A scanning electron microscope automatic process inspection approach, which is non-destructive and proven to be effective, has been established to image the fin defects at the bottom of the trench. A possible root cause of this defect is also explored. Both simulation and benchmarking test results indicate that bulk micro defects (BMDs) in the silicon substrate could serve as a micro-mask during etching and result in silicon fin defects.

3D integration technology offers an alternative to traditional packaging designs. In traditional Moore's law scaling, features are added to the die, with graphics, memory control and logic coprocessors all integrated onto the silicon chip. TSV (through silicon via) processing utilizes vertical electrical interconnects that provide the shortest possible path to establish an electrical connection from the device side to the backside of a die. This indirectly allows continues "Moore"- like scaling while only affecting the device packaging.White light interferometry (WLI) has been used for the measurement of topography, step height and via depth using its short coherence length. The nanometer level resolution of this technique is ideal for TSV measurements in the high aspect ratio vias.In this work, six white light interferometer measurements for TSV processing are discussed along with the importance of these measurements to TSV processing, namely:1. Post-TSV etch: depth, top CD (TCD) and bottom CD (BCD)2. Post-TSV liner BCD3. Post-TSV barrier seed BCD4. TSV electro-chemically plated (ECP) copper bump step height5. Post-annealing bump step height6. TSV CMP dishingThese measurement steps have been implemented in-line for advanced technology node TSV process flows at GLOBALFOUNDRIES. The measurements demonstrate 90% correlation to reference metrology and <0.5% repeatability. Cross section SEM was used as a reference for TSV profile and Cu bump measurements while AFM was used as a reference for dishing measurements.