We report a study on moisture effect on optical performance of monolithic silicon photonics technologies featuring V-grooves for self-aligned fiber attach. Chip-level hermetic sealing was achieved by implementing moisture barrier for the fiber coupler.

The acceptance of Wafer Level Chip Scale Package (WLCSP) technology is significantly increasing for use in small devices such as mobile phones, wearable, RF antenna packages, and health monitor sensors. WLCSP structures can have a few thin redistribution layers (RDLs) between the chip surface and the printed circuit board (PCB), or the interconnectors can be placed in direction connection to the back end of the line (BEoL). Due to the high coefficient of thermal expansion (CTE) mismatch between the silicon chip and the organic laminate, the WLCSP chip's board level reliability (BLR) can present a significant challenge. In this paper, BLR tests applying different board trace and bump array designs are discussed for a 45nm RFSOI WLCSP package. A fatigue model is developed utilizing the BLR qualification tests and numerical simulation is then used to correlate the BLR experimental data. A newly improved test vehicle configuration was built based on learning from the BLR test and FEM learning. The result shows significantly improved solder joint lifetime when compared with the initial design.

Front and back ends of line (FEOL and BEOL) self-heating and mutual heating are important barriers to a sustained increase in processor speed and density. In this context, the severity of transient Joule heating in scaled interconnectsunder a variety of operating conditions (e.g., frequency and duty cycle) is not fully understood. Herewe introduce the closed-formanalytical transient Joule heating model to calculate the time-dependent temperature rise of an interconnect(Delta T-Int(t)) located at an arbitrary metal level within an integrated circuit (IC). The model is validated by high-fidelity finite element method simulations and specially designed test structures. Remarkably, the model predicts I-Max (the interconnect-specific current for a certain degree of Delta T-Int) within 20%-25% for an arbitrary duty cycle. Therefore, our model can be used to accurately predict temperature-accelerated interconnect reliability issues of a modern IC.

The MOL PC-CA TDDB reliability is systematically evaluated for the 1.98V IO devices with Self-Aligned Contact (SAC) and top off oxide process. Compared to the thin oxide devices, significant reliability improvement from both t63 and β can be achieved by tuning the top off oxide thickness thus making it fully compatible with the SAC process flow, with no impact to device and device reliability performance.

Lower RC delay is vital to achieve optimal and competitive circuit performance and hence drives the endlessly pursued BEOL integration scheme advancement. To date low-k dielectric materials, i.e., fluorine-doped oxides, carbon-doped oxide (SiCOH), to porous carbon-doped oxides (p-SiCOH) have been implemented. However, due to the process integration challenges with inherently weak low-k materials, the trend to pursue lower k dielectrics has come to a plateau as technology nodes scale down past 20/14nm. On the other hand, the trend of geometry layer thickness shrinking down, such as trench CD and height, via CD and height, etc., still continues for each advanced technology node. In the BEOL stack adhesion layers (oxide + gradient layers) (ALs) with higher k value were introduced to enhance interface adhesion strength between SiCOH/p-SiCOH and dielectric cap film (SiCN), which offset the intrinsic RC benefit from low-k dielectric material. At more advanced nodes and beyond, the combined ALs and cap film could be up to via or trench height, which poses a huge challenge to meet desired RC performance and technology node scaling. Therefore, the thickness reduction of ALs and cap film becomes necessary for further technology node scaling. In this study, samples with interfacial full ALs, reduced ALs and bulk only (no ALs) for p-SiCOH (k=2.75) on various cap films were prepared, such as SiCN, SiCN/ODC, SiCN/AlONx, etc. TOF-SIMS analyses was used to confirm the composition of the dielectric stacks and later check the debonded surface morphology. Four-point bend adhesion tests were conducted to evaluate interfacial adhesion strength. Results show the interfacial adhesion strength on samples with reduced Als and bulk only (no ALs) is dropped by ~20% and ~30%, respectively. Additional ODC layer on top of SiCN would increase the interfacial adhesion strength by ~10%. It is suggested that reduced ALs may be adequate to satisfy overall CPI requirement for the BEOL integration scheme of p-SiCOH on advanced dielectric cap films (AlN + ODC). The coupling capacitance reduction for a combined reduced ALs and advanced dielectric cap can be up to 16% at M0 level and 10% at Mx level for a 40nm metal pitch.

Stacking of chips vertically will reduce the interconnection resistance and as a result enhance data communication between chips. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC type chip level integration. Memory to logic integration can be done side by side using a silicon interposer, known as 2.5D integration. Copper filled through Silicon via (TSV) in a silicon wafer is the key enabling technology for this integration. In this paper 100um thin silicon interposer is fabricated with a 3 BEOL (Back end of line) metal process having TSV with 10um diameter. A standard interposer and a stitched interposer reliability challenges are described in this paper. Wafer level reliability of the interposer is studied with electromigration and stress-migration.

Temperature is one of the most sensitive factors for device and interconnects reliability, especially for Electromigration (EM). A 5°C temperature rise in metal line will induce a 30% EM lifetime decrease [1]. In order to achieve good EM lifetime, Root Mean Square of current (Irms) rule was designed to limit interconnects temperature rise induced by self-heating. Peak current (Ipeak) rule was also designed to prevent sudden temperature rise caused by instantaneous high current. Previous study reported [2] a high frequency pulse current (PDC) resulted in lower joule heating (JH) compared to an equivalent steady state condition. However, the effect of very high frequency (1GHz~1THz) with various duty ratios is still unclear. In this paper, both experimental measurement and finite element method (FEM) simulation approach were used to investigate the impact of temperature rise due to JH by high frequency PDC with various duty ratios. Special thermal test macros using 64nm pitch double patterning LELE technology have been implemented to study frequency and duty ratio effects on JH. Metal width effect was investigated as well. A waveform generator measurement unit was used to measure the resistance profile under different frequency waves. Temperature change was estimated using the temperature coefficient of resistance (TCR). Finite Element Model (FEM) was built based on process assumption, metal width and via profile which were verified by cross section measurement. The FEM model was validated by experimental data in intermediate frequency range, and then used to study very high frequency situation, which cannot be handled by experiment. It was found that high frequency can suppressed Joule heating in metal line. But it also limited metal line to cooling down when power is off. For very high frequency PDC, peak/bottom temperatures approach constant temperature, which is frequency independent. This constant temperature can be determined from steady state thermal model. Reducing duty ratio can control device turn on time thereby reducing peak and average temperature.

Non-Poisson area scaling behavior has long been observed in BEOL (Back End Of Line) and MOL (Middle Of Line) Time-dependent dielectric breakdown (TDDB) reliability tests due to known variations across the wafer. Three different statistical models have been proposed to accurately account for this non Poisson behavior. In this work, a new methodology for proper area scaling treatment is systematically studied by both experiments and Monte Carlo simulations. A more realistic and robust method is then proposed, for a more accurate reliability projection.

Stacking of chips vertically will reduce the interconnection resistance between the chips and also enhance data communication between them. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC type chip level integration. Memory to logic integration can be done either 2.5D or 3D architecture. Wafer with Through Silicon Via (TSV) is the key enabling technology for this integration. 2.5D is in a nonfunctional wafer while 3D is in a functional wafer. Reliability is a key requirement in accomplishing this complex integration of TSV wafer for both 3D and 2.5D architecture. Wafer level intrinsic reliability for 2.5D and 3D has been studied with respect to BEOL test structures (for EM, TDDB and SM) and to FE OL structures (for TDDB, HCI, BTI and PID). Unique challenges in meeting the reliability of these two complementary technologies are described in this paper.

To enable higher computing power in a single chip, there is demand for increasing die size for high performance applications in advanced nodes. Due to the weak mechanical properties of the low-k and ultra low-k (ULK) dielectrics in advanced technology nodes, the backend of line (BEOL) stacks are more prone to thermal mechanical failures, resulting in increased semiconductor assembly processes and reliability challenges. This is further exacerbated by the transition of lead (Pb) based solders to Pb-free solders ( higher melting temperatures), as well as the transition to copper pillar bump (less malleable / deformable). These changes bring more package stress which can potentially be transferred to the BEOL stack, increasing chip-package interaction (CPI) failure risks. With the increased distance to neutral point (DNP) in large dies, the package to die stress also increases significantly. Therefore, CPI risks in large die applications in advanced nodes are especially challenging. This paper discusses in detail the different CPI reliability challenges of large dies with size up to 25mm x 25mm in flip-chip ball grid array (fcBGA) packages in an advanced CMOS technology node. One of the key findings from this study is the impact of kerf width (crack stop to crack stop distance) on CPI performance. While it is well known that narrow kerfs are more subject to dicing damage risks, it is less recognized that wide kerf poses unique CPI challenges. Both narrow and wide kerf were assessed in this work. It is observed that narrow and wide kerf can drive different failure mechanisms. A wide kerf is especially challenging for CPI due to increased energy release rate of cracks if present. By understanding the physics and mechanics of failures, key CPI sensitive parameters can be defined to ensure products are robust to successfully meet various industry standard CPI stress qualification.

The impact of wafer level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) reliability. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) behavior indicates that there is negligible impact on Idsat due to mechanical stress of the TSV for 5 μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed at 25°C and 125°C to study the FEOL gate dielectric and device reliability such as gate dielectric breakdown voltage (VBD), Hot Carrier Injection (HCI), and Bias Temperature Instability (BTI). Apart from FEOL reliability study, special test structures were also designed to capture even a minor TSV impact on the lower metal and via levels of the BEOL stack. Time Dependent Dielectric Breakdown (TDDB), Electro migration (EM), and Stress Migration (SM) were performed to investigate any potential impact to BEOL due to TSV mechanical stress or Cu pumping effects. TSV KOZ impact on electrostatic discharge (ESD) protection devices was also performed. Our study with thick and thin TSV wafer showed no significant impact of TSV integration approach on FEOL, BEOL and ESD reliability.

Electromigration reliability of BEOL Cu interconnects with various metal line widths and via sizes has been studied. EM lifetime significantly improves from minimum width to three times the minimum width, and then saturates. In addition, the EM lifetime of the wide metal lines was not dependent on via size. The proposed mechanism for EM lifetime improvement is larger grains in wider lines leading to a suppression of grain boundary diffusion. Cu grain size and Cu drift velocity were correlated to the EM lifetime behavior, saturating at the same line width, and kinetic studies found activation energies consistent with grain boundary diffusion.

Cracks at the die edge induced by dicing can grow due to chip-package interaction (CPI) and thermal cycling experienced in service. The semiconductor industry has been making major efforts to prevent die edge cracks from propagating into the active area of a chip. Patterned metal structures are commonly introduced around the perimeter to play a role as crackstop by increasing the fracture resistance near the die edge. In advance technology nodes, while the introduction of ultra low-k (ULK) materials reduces the RC delay, it also adds to the CPI challenge due to its weaker mechanical strength and fracture resistance. Die edge cracking risk is thus still a major reliability concern. In this report, a structured methodology that can address the die cracking reliability challenges is presented. Experimentally, we found that the effectiveness of crackstop structures for arresting dicing crack propagation depends on the following aspects: (1) BEOL stack, (2) crack stop design, (3) dicing location, (4) substrate. In this paper, multilevel finite element method (FEM) simulations are conducted to provide fundamental understanding of the failure mechanism. Cohesive zone modeling (CZM) is implemented in the last level of submodel to simulate the dicing crack propagation. A fracture mechanics-based methodology is implemented to calculate the crack driving force (energy release rate) and identify the weakest layer in the BEOL stack. The effect of BEOL stacks, packaging stress, and crackstop location are investigated thoroughly to study key drivers of the various die edge cracking behaviors observed experimentally. We demonstrate that the methodology presented herein can be used to investigate die edge cracking risks for future advanced technology nodes.

Recently a BEOL (Back End Of Line) and MOL (Middle Of Line) Time-dependent dielectric breakdown (TDDB) reliability test and fail rate projection methodology based on large data analysis was proposed and studied. However the extraction of one of the key model parameters, the field acceleration factor Y e was ambiguously defined. If no enough caution is taken, a systematically lower γ E will be obtained which leads to a pessimistic projection. In this work, the fundamental differences with two different extraction methods are systematically studied by both experiments and Monte Carlo simulations. A more realistic and robust method is then proposed, for a more accurate reliability projection.

Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.

Spatially resolved precise prediction of local temperature T(x,y,z) is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, especially for fast turn-around reliability modeling. Here, an analytical model that can quickly/accurately determine T(x,y,z) will reduce the design time of self-heated modern IC. In this paper, we 1) develop a physics-based electrothermal compact model for ICs to predict T(x,y,z) based on the synthesis of effective medium theory, image charge theory, and Rent's rule; 2) validate our model against 3-D FEM and experimental data; and 3) predict back-end-of-line (BEOL) reliability (i.e., electromigration at each layer) based on the temperature profile. Since our analytical model predicts changes in T(x,y,z) with any given IC's configuration (e.g., interconnect wire length and number distribution, metal volume fraction in BEOL, heat sinks mechanisms, materials, and type of devices), it suggests new opportunities for optimization of performance and reliability of modern ICs.

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

Low-κ SiCOH reliability is a growing concern for integrated circuit reliability. An important consideration for product qualification involves the accurate extrapolation to the low percentile failures based on the results from a group of samples. A method is presented to determine the root cause of failure distributions amongst a group of dielectric samples using voltage ramp data. Samples' leakage current traces and breakdown voltages are compared with each other. Using this method, it was determined that the dielectric spacing variation dominates across-wafer failure, while variation of local breakdown strength affects in-chip failure.

Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.