In this work, we investigate 10-keV X-ray-induced total ionizing dose (TID) effects in vertical p-in (VPIN) photodiodes (PDs) using calibrated TCAD simulations. We demonstrate that positive trapped charges near the space-charge region locally increase the electric field magnitude, enhancing Shockley-Read-Hall (SRH) generation-recombination and trap-assisted tunneling (TAT) rates, thereby impacting dark current, forward current, and the ideality factor. Simulations indicate that charge trapping at the top-corner Ge/SiO2 interfaces accurately reproduces experimental trends. In contrast, photocurrent and junction capacitance remain largely unaffected, attributed to the large area-to-perimeter ratio of the device, which reduces the influence of localized interface degradation.

This work investigates the waveguide-integrated vertical p-i-n (VPIN) germanium-on-silicon (Ge-Si) photodiodes under 10-keV X-ray irradiation to evaluate the impact of geometrical features, implant design, and bias during irradiation on total ionizing dose (TID) response. The use of localized p+ contact implantation for high efficiency leads to heightened TID sensitivity, due to ionization-induced oxide trapped charges at the top Ge/SiO2 interface. This more than doubles the dark current, as compared to designs with continuous contact doping. The TID-induced response of each photodiode design is strongly influenced by bias during irradiation, with increases in dark current up to similar to 100% for -2 V bias, compared to grounded test conditions. This increase is due to electric field enhancement near the Ge/SiO2 interface, as demonstrated by technology computer-aided design (TCAD) simulations. The application of forward bias after irradiation leads to swift annealing of TID effects and partial performance recovery due to injection-enhanced tunneling near the Ge/SiO2 interface. The observed dark current sensitivities and mitigation by forward bias annealing suggest that Ge-Si photodiodes are well-suited for applications in high-radiation environments.

As pertains to the physical comprehension of defect dynamics in large-area dielectrics, established methodologies, such as time-dependent dielectric breakdown (TDDB) and stress-induced leakage currents (SILC), typically provide insufficient insights. Here, we capitalize on noise spectroscopy to investigate degradation phenomena in 5 nm plasma-enhanced chemical vapor deposited (PECVD) SiCN films. We leverage kernel methods to estimate the exact statistical distribution of the fluctuation time series, which we subsequently analyze through its moments up to fourth order. The highest-order moment is identified to be the most representative measure of the defects' stress response in PECVD SiCN films, at varying voltages and temperatures, constituting a robust and reliable degradation metric.

An electrothermally induced resistance modulation in advanced high-speed Ge photodetectors under nanosecond electrostatic discharge (ESD) events is investigated through measurements and physics-based models. By employing a very-fast transmission line pulsing (VF-TLP) test system, the measured I-V characteristics reveal that the differential resistance-lowering (DRL) effect is triggered under a 1-ns pulse duration, consistent with temperature-dependent intrinsic carrier density behavior and TCAD simulation results. Among the evaluated devices, the vertical Ge photodetector (VPIN) exhibits the most pronounced DRL behavior, attributed to its device geometry. Understanding these mechanisms can help improve ESD robustness and enhance the reliability of next-generation high-speed silicon photonic technologies.

We report forward bias and temperature-dependent low-frequency (LF) noise characteristics of waveguide-integrated Ge-on-Si p-i-n photodiodes across three architectures: doped-Si lateral, doped-Ge and doped-Si lateral, and vertical heterojunctions. Forward I-V measurements and activation energy analysis reveal mixed Shockley-Read-Hall recombination and diffusion transport below 0.4 V, with transport ratios evolving more gradually with temperature in vertical devices than in lateral devices. At room temperature, the noise spectra exhibit broad generation-recombination (G-R) features near V = 0.2 V, aligning with the transition from G-R-dominated ( S-I similar to I-2 for V <= 0.2 V) to diffusion-limited ( S-I similar to I for 0.2 V <= V <= 0.5 V ) current noise. Technology computer-aided design simulations indicate that in lateral devices the defect-rich Ge/Si interface lies within the depletion region, where interface traps strongly enhance G-R noise. In vertical devices, the Ge/Si interface is located outside the depletion zone, so the noise response is dominated by bulk Ge traps. Temperature-dependent measurements reveal a smooth transition from G-R noise below 300 K to diffusion-type flicker noise at higher temperatures. Notably, normalized noise S-I /I-2 peaks around 300 K in lateral devices, marking a crossover in dominant noise mechanisms. Observed increases of low-temperature noise after total-ionizing-dose irradiation in lateral devices result from the electrostatic activation of traps within the narrow depletion region, whereas the increase of forward current originates mainly from radiation-induced additional leakage paths. These results establish LF noise spectroscopy as an effective tool for probing interfacial defect dynamics in Ge-on-Si photodiodes. (c) 2025 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license(https://creativecommons.org/licenses/by/4.0/).

On-chip germanium-silicon (Ge-Si) photodiodes are critical elements in advancing the inclusion of silicon photonics in integrated circuit design. Understanding their radiation tolerance is essential for use in instrumentation that is operated in harsh environments, where the benefits of photonic integrated circuits (PICs) on performance and compactness are increasingly advantageous. Effects of contact configuration and geometry on waveguide-integrated Ge-Si photodiodes under 1.8-MeV proton and 10-keV X-ray irradiation are studied. Modest operating dark current increases up to 35 nA or 4.25 dB resulting from nonradiative defect center generation and ionization-induced traps. Radiation sensitivities are compared to thermal effects on performance, supporting the relative robustness of Ge-Si photodiodes to radiation. Annealing testing is performed to evaluate interface trap stability due to total ionizing dose (TID), which is dependent on the specific design of the photodiode. The increases in photodiode noise floors are modest overall but are important to design strategies for space and accelerator environments, especially as performance requirements and circuit complexity of integrated photonic technologies increase.

The combined effect of thermomigration (TM) and electromigration (EM) on the reliability of Cu interconnects is investigated. Package-level EM+TM tests were conducted to understand the impact of temperature gradients on void nucleation and void growth in the presence of electrical currents. Through failure analysis, void nucleation at the via bottom followed by subsequent void growth toward adjacent vias is confirmed. An analytical model is developed to quantify the impact of temperature gradients on EM lifetime. Results indicate that thermal gradients have a more pronounced impact at lower ambient temperatures, reducing EM lifetime by approximately 50% at 100 degrees C, compared to a 42% reduction at 300 degrees C. This work enhances the understanding of EM+TM coupling mechanisms and provides a practical model for predicting Cu interconnect reliability under combined stress conditions.

Recommended practices for SiPho heater qualification and design are outlined. Regarding heater qualification, the importance of proper thermal modelling and failure analysis to accurately determine the failure location and its temperature is highlighted. Also, it is motivated that properly accounting for thermal gradients at the failure location is crucial for a proper lifetime extrapolation. It will be shown that only by considering these two items (temperature at failure location and thermal gradients), accurate lifetime predictions can be obtained. Regarding heater design, potential ways to slow down failures and to decrease the temperature at the failure location are discussed.

This study investigates electromigration in a double-redundancy interconnect configuration, commonly found at standard-cell level in the power delivery networks, under downstream electron flow conditions, using both experiments and physics-based simulations. This work sheds light on the critical jL product, (jL)c, in presence of a parallel path. Due to double redundancy, for our samples coming from a 28nm commercial technology node, the critical current density jc was found to increase by 1.15-fold and 1.1-fold, for 5% and 20% R-shift failure criteria, respectively. The impact of line extension on (jL)c was also investigated. A 37% decrease in (jL)c was observed for a single line with a passive line extension acting as a sink, undermining the short-length effect, regardless of the failure criterion. For the same target lifetime, a 1.2-fold increase in maximum allowable current density, based on a 50% target failure percentile and 10 years lifetime criterion, was obtained when comparing the single and double redundancy configurations for 5% R-shift.

Dielectrics are fundamental building blocks in both analog and digital electronic devices, serving various purposes, including insulating metal lines and interconnect levels in the back-end-of-line (BEOL). In this article, we investigate the leakage and low-frequency noise (LFN) properties of three different types of dielectrics, from the low-k organo-silicate glass (OSG3.0) and silica (SiO2) to the high-k alumina (Al2O3). Test structures are large area (up to 200 x 200 mu m(2)) metal-insulator-metal (MIM) capacitors, with TiN or TaNTa electrodes, that mimic well the BEOL architecture. In particular, to the best of our knowledge, no LFN study has been reported for OSGs, which are the most used class of dielectrics in the BEOL. From a physical side, current-voltage (I-V) characterization reveals that in all three dielectrics, the conduction is bulk dominated and assisted by traps, rather than limited by electrode injection. LFN measurements (LFNMs) show a typical 1/f current power spectral density (PSD) (SI) for all three dielectrics with a strongly bias-dependent gate noise parameter (GNP) proportional to SI/I-2 (I being the dc current), suggesting a highly nonuniform energy trap distribution, especially for Al2O3 devices. SiO2-based capacitors demonstrated the lowest leakage at equivalent fields and superior noise performance at comparable leakage currents. Al2O3 devices exhibited the highest leakage, while OSG3.0 samples showed the poorest noise characteristics, marked by pronounced electrical instability and nonstationary random telegraph signal (RTS) events.

As the electromigration (EM) reliability margin reduces rapidly with scaling, novel approaches for EM-compliance checks are being intensively sought to enable more accurate and less conservative analyses. Currently, chip-level EM reliability is assessed based on the failure probability of individual lines and vias in the BEOL stack, overlooking potential redundant connections that could still ensure circuit operation despite isolated failures. This is particularly relevant for the power delivery network (PDN), which is redundant by definition due to its regular mesh structure. In this work, we leverage a new approach to perform EM-compliance checks that relies on considering the PDN as a matrix of identical network units-cells, henceforth referred to as tiles, and using them to compute the overall failure risk. As opposed to conventional methods, our approach captures the impact of redundancy within each individual PDN tile, thereby providing less conservative reliability estimations. After reviewing standard methods for EM-compliance checks, namely limit-based and statistical EM budgeting (SEB), we quantify the additional reliability margin provided by our PDN-tile approach. For our analysis, we considered a PDN featuring three different metallization schemes for Dual Damascene (DD) Cu/Low-k interconnects utilizing SiCN capping, Cobalt (Co) capping with and without Ruthenium (Ru) via prefill. Using the standard SEB method indicated that Co capping and Co capping + Ru Via Prefill lead to reductions in EM failure risk by 5 and 7 orders of magnitude, respectively, compared to SiCN capping. The new approach was implemented for the first metallization with SiCN capping. At 10 years lifetime, our PDN-tile approach foresees a failure probability which is 3 orders of magnitude smaller than the SEB approach. At an equivalent failure probability of 100ppm and the same target lifetime of 10 years, the current of standard cells can be increased by 2.8-fold, giving designers more margin to improve chip performances.

On-chip germanium-silicon (Ge-Si) photodiodes are critical elements to advancing the inclusion of silicon photonics in integrated circuit design. Understanding their radiation tolerance is essential for use in instrumentation that are operated in harsh environments, where the benefits of photonic integrated circuits on performance and compactness are increasingly advantageous. Effects of contact configuration and geometry on waveguide-integrated Ge-Si photodiodes under 1.8-MeV proton and 10-keV X-ray irradiation are studied. Modest operating dark current increases up to 35 nA or 4.25 dB result from nonradiative defect center generation and ionization-induced traps. Radiation sensitivities are compared to thermal effects on performance, supporting the relative robustness of Ge-Si photodiodes to radiation. Annealing testing is performed to evaluate interface trap stability due to total ionizing dose, which is dependent on the specific design of the photodiode. The increases to photodiode noise floor are modest overall but are important to design strategies for space and accelerator environments, especially as performance requirements and circuit complexity of integrated photonic technologies increase.

Through physical and electrical analysis, the impact of thermal gradients on mass transport in Cu interconnects is studied using a dedicated test structure. The key physical parameter for thermomigration (TM), the heat of transport (Q∗), is evaluated experimentally to be 0.21 eV. Furthermore, an analytical model based on existing 1D physics-based models [M. A. Korhonen et al., J. Appl. Phys. 73, 3790–3799 (1993); H. Zahedmanesh et al., Microelectron. Reliab. 111, 113769 (2020)] is proposed to predict the time to void nucleation, the void growth rate (νgrowth), and the time to failure (TTF) due to TM. Also, their dependence on temperature (T), temperature gradient (dTdx), and second derivative of the temperature (d2Tdx2) is derived. This analytical model calibrated using experimental data predicts a TTF of 38 years for a 1μm wide Cu interconnect under specific stress conditions: an operating temperature of 100°C, a local temperature increase of 67°C, and a d2Tdx2=−2.9°C/μm2 induced by an external heat source.

The traditional techniques for extracting polycrystalline grain structures from microscopy images, such as transmission electron microscopy (TEM) and scanning electron microscopy (SEM), are labour-intensive, subjective, and time-consuming, limiting their scalability for high-throughput analysis. In this study, we present an automated methodology integrating edge detection with generative diffusion models to effectively identify grains, eliminate noise, and connect broken segments in alignment with predicted grain boundaries. Due to the limited availability of adequate images preventing the training of deep machine learning models, a new seven-stage methodology is employed to generate synthetic TEM images for training. This concept-oriented synthetic data approach can be extended to any field of interest where the scarcity of data is a challenge. The presented model was applied to various metals with average grain sizes down to the nanoscale, producing grain morphologies from low-resolution TEM images that are comparable to those obtained from advanced and demanding experimental techniques with an average accuracy of 97.23%.

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

A calibrated simulation framework for the analysis of electromigration (EM) in nano-interconnects, incorporating the intricate influence of microstructure, is presented. Different technology options were benchmarked for EM performance, taking copper texture and microstructural changes with scaling into account. Specifically, the impacts of metal cap and copper doping were simulated for a constant line height of 80nm and for linewidths between 20 and 100nm. An almost linear increase in normalized lifetime was observed for aspect ratios of 1 and above. An increase ranging from 10x to 100x was gained by using a metal cap for aspect ratios below 2. However, its effectiveness strongly weakened with decreasing CD with almost no EM lifetime gain for 20nm CD. Doping elements that lower grain boundary diffusivity were found to be more effective at these small dimensions.

A comprehensive ESD robustness study of 5 different Ge photodetectors in advanced Si photonic technology is presented. The measurement results disclose that the main impact on the ESD transient IV characteristics is from the contact location of the anode terminal. Still, the failure mechanisms need to be further clarified by physical failure analysis as a part of the future work.

In this article, the reliability assessment of a 2.5-D metal–insulator–metal (MIM) capacitor, built in a thicker back-end of line layer using a 23-nm-thick ALD-deposited Al-doped HfO $_\text{2}$ high- $\kappa$ dielectric, is performed using time-dependent dielectric breakdown (TDDB) measurements. This capacitor, compatible with back-side power delivery network (PDN) technologies, presents a density above 16.7 nF/mm $^\text{2}$ while retaining a leakage current lower than 0.3 pA/nF at 2 V and 100 $^{\circ}$ C. It offers a quadratic voltage coefficient of capacitance around 500 ppm/V $^\text{2}$ at 25 $^{\circ}$ C and a temperature coefficient of capacitance of 191 ppm/ $^{\circ}$ C. The breakdown field of this high- $\kappa$ dielectric is around 6.2 MV/cm at 25 $^{\circ}$ C. The thermochemical formalism commonly used to describe dielectric breakdown was unsuccessfully tested on this device, confirming the joint contribution of current and field in the degradation process. In addition, the time to failure (TTF) temperature dependence is found to follow an Arrhenius mechanism. Assuming a power law (PL) extrapolation model, 800-mm $^\text{2}$ capacitors are expected to survive ten years with a failure rate lower than 1 ppm when operated at 100 $^{\circ}$ C using voltages below or equal to 2.22 V.

This study presents an innovative approach to characterize the reliability of back-end-of-line (BEOL) dielectrics, particularly focusing on the breakdown between metal tips. By using a design-representative test structure, we implement a novel experimental procedure, referred to as “double V -ramp stress”, to discriminate between various failure modes, including line-to-line (L2L), via-to-line (V2L) and tip-to-tip (T2T) breakdowns, and distinctly investigate them. The procedure involves a 4-point voltage stress analysis, where leakage currents at different terminals are meticulously monitored to electrically identify the failure modes at play. Our findings highlight the critical importance of T2T spacing control for enhancing T2T dielectric reliability. We provide insights into the behavior of dielectrics under varied stress conditions, which is key to enable further dimensional scaling of VLSI technologies.