In this study, a simple, reliable, and universal circuit model of bipolar resistive-switching random-access memory (RRAM) is presented for the circuit-level simulation of a high-density cross-point RRAM array. For higher accuracy and reliability, the compact model has been developed to match the measurement data of the fabricated RRAM devices with SiN_x and HfO_x switching layers showing different reset switching behaviors. In the SPICE simulation, the RRAM cross-point array is virtually realized by embedding the empirically modeled memory cells, by which device performances such as read margin and power consumption in the high-density array are closely investigated.

In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time ( ${T}_{\text {write}}$ ) and erase time ( ${T}_{\text {erase}}$ ) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 10 5 . Also, ${V}_{\text {write}}$ and erase voltage ( ${V}_{\text {erase}}$ ) of the 2-T TRAM appear to be below 2 and −1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal-oxide-semiconductor (CMOS)-compatible Ti/SiNx /p+ -Si memristor by simply reducing the cell size down to sub-100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub-100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low-resistance state is attributed to Fowler-Nordheim tunneling dominating in the high-voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal-nitride-silicon memristor device paves the way to realize CMOS-compatible high-density crosspoint array applications.

In this work, the simultaneous detection of threshold switching and bipolar memory switching in Ag/SiNx/p++-Si devices is investigated. In the DC sweep mode, threshold switching is observed with low compliance current limit (CCL) of 1 μA while memory switching is dominant when high CCL (1 mA) is applied. It is found that in the pulse switching mode, pulse amplitude is an important factor in determining the nature of switching. It has been proven that the strength of the Ag filament formed in the SiNx determines the nonvolatile property of the switching. The undirectional threshold switching behavior in low currents of Ag/SiNx/p++-Si devices could be used as a selector for a low-power unipolar memory. Moreover, operating in two modes in one device will provide more flexibility in device design.

This paper proposes a 3-D floating-gate (FG) synapse array for neuromorphic applications. The designed device has certain advantages over previous planar FG synapse devices: a smaller cell size due to the stacked structure and smaller operation voltage by the gate-all-around geometry. In addition, the operation method to implement spike time-dependent plasticity is proposed and demonstrated. The proposed array based on commercialized flash memory technology is expected be one of the most promising candidate architecture for neuromorphic applications.

In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that the overall system performance of large HPC clusters is not particularly sensitive to main-memory latency. Therefore, STT-MRAM, as well as any other emerging non-volatile memories with comparable density and access time, can be a viable option for future HPC memory system design.

In this work, the effects of conducting defects on resistive switching characteristics of SiNx-based resistive random-access memory (RRAM) have been investigated. Two types of RRAM devices having metal–insulator–silicon layer configuration were fabricated. One is the device with SiNx as the resistive switching layer deposited by plasma-enhanced chemical vapor deposition (PECVD), and the other has the SiNx layer prepared by low-pressure chemical vapor deposition (LPCVD). The device cell deposited by LPCVD (LP-SiNx cell afterward) demonstrated superior uniformity of switching parameters and better endurance cycles compared with the device cell deposited by PECVD (PE-SiNx cell afterward).

The spike-timing dependent plasticity (STDP) of biological synapses, which is known to be a function of the formulated Hebbian learning rule of human cognition, learning and memory abilities, was emulated with two-phase change memory (2-PCM) cells built with 39nm technology. For this, we designed a novel time-modulated voltage (TMV) scheme for changing the conductance of 2-PCM cells, that could produce both long-term potentiation (LTP) and long-term depression (LTD) by applying variable (decreasing/increasing) pulse voltages according to the sign and magnitude in time interval between pre- and post-spikes. Since such schemes can be easily modified to have a variety of pulse shapes and time intervals between pulses, it is expected to be a proper scheme for designing diverse synaptic connection abilities. In addition, the small form factor and low energy consumption of 2-PCM make them comparable to biological synapses, which makes phase change memory a promising candidate for electronic synapses in large-scale neuromorphic system applications.

The conduction mechanism in Ti/Si3N4/p-Si memory stack is described. In order to analyse the conduction mechanism, we have measured the I V characteristics in voltage sweep mode and performed I-V curve fitting. The temperature dependence in Ti/Si3N4/p-Si stacked cell has also been investigated because we cannot identify the conduction mechanism just based on the I-V curve fitting. From I-V curve fitting and temperature measurement data, we have found that space charge limited conduction (SCLC) model is the most probable mechanism in both high resistance state (HRS) and low resistance state (LRS).

The conduction mechanism in Ti/Si3N4/p-Si memory stack is described. In order to analyze the conduction mechanism, we measured the I-V characteristics in voltage sweep mode and conducted I-V curve fitting. And the temperature dependence in Ti/Si3N4/p-Si stacked cell is also investigated because we cannot claim the conduction mechanism just based on the I-V curve fitting. From I-V curve fitting and temperature measurement data, we found that space charge limited conduction (SCLC) model is well fitted in both high resistance state (HRS) and low resistance state (LRS).

In this paper, bipolar resistive switching was investigated in our fabricated Ti/Si3N4/p+-Si resistive random access memory (RRAM) devices. Heavily doped p-type Si was used instead of a conventional bottom electrode (BE) using metal such as Pt. We found that forming-free process, self-compliance and gradual reset were shown in this device. The operation voltage was with 1.8~3.5 V during set process due to forming-free process. And self-compliance was observed by restriction of parasitic resistance without external current limiter. Finally, multi-level cell (MLC) feasibility was achieved using voltage stop during gradual reset.

We emulate the spike-timing dependent plasticity (STDP) behavior of biological synapse in two phase change memory (2-PCM) cells with 3x nm technology, which has been considered as a formulated Hebbian learning rule of our cognition, learning and memory abilities. Various STDP behaviors are successfully realized in 2-PCM synapse by varying the interval of set pulses on two cells and their pulse shape as well, which helps to design diverse synaptic connection abilities. In addition, its small form factor and low energy per synaptic event compared to conventional silicon neuron networks (SiNs) make very promising candidate for electronic synapse in the large-scale neuromorphic system applications.

To analyze and explain the gradual reset switching property of the bipolar switching resistive random access memory (RRAM) for multilevel cell (MLC) operation, the effect of the amount of plasma oxidation on the gradual reset switching behavior of the Al/TiO2-based RRAM cell structure is investigated. The device that undergoes plasma oxidation in a shorter time has a better ON/OFF current (ION/IOFF) ratio and shows increased ON current (ION). The device that undergoes long plasma oxidation occasionally shows the step reset switching behavior because of the thick conductive filament formation in the ON state. This is clearly explained by the different conduction mechanisms during the ON state.

An interface-engineered resistive random access memory (RRAM) using bilayer transition metal oxide (TMO) is presented for improving unipolar resistive-switching characteristics. The experiment and simulation data show that better resistive switching characteristics and superb uniformity can be realized by inserting a thin AIOx insertion layer between the Ir/NiO interface. To elucidate the uniformity improvement of our bilayer structure, the conducting-defect effects in the resistive cell were also investigated using a random circuit breaker (RCB) simulation model. It has been verified that the forming and set characteristics are more effectively improved because the conducting-defect ratio in the insertion layer region is low, therefore making it more advantageous for a filament path controllability. Using the optimal oxygen contents in both the insertion layer and the resistive cell, it was confirmed that a significant reduction of up to 0.15 mA of the reset current (I(RESET)) is possible compared to the conventional cell. These results indicate that new AI insertion has a large contribution to the reset and forming processes.

We firstly propose a novel resistive random access memory (RRAM) cell structure, which makes it possible to minimize the switching area and to maximize the electrical field where resistive switching occurs, resulting in the improvement of resistive switching characteristics. With excellent structural advantages, resistive switching characteristics such as reset current and set voltage fluctuation are improved through the enhancement of conductive filament (CF) controllability. A simple fabrication process is delivered and the device performance from the viewpoints of the forming voltage, set voltage, and reset current is investigated. Conducting defect effects are also investigated in comparison with the conventional RRAM cell structure. Numerical simulation is performed using a random circuit breaker (RCB) model to confirm the proposed structure.