As complementary metal-oxide-semiconductor (CMOS) scaling slows and artificial intelligence (AI) demand soars, atomic-scale platforms such as quantum-dot logic based on silicon dangling bond (SiDB) offer a promising path toward energyefficient computation, yet practical design flows from registertransfer level (RTL) specifications to manufacturable layouts remain limited. This work presents an RTL-to-atoms synthesis framework for a quantized matrix multiply unit (MXU) targeting SiDB-based field-coupled nanocomputing (FCN). Building on recent advances in SiDB-aware electronic design automation (EDA), the framework combines a hierarchical, parameterized RTL architecture with platform-optimized arithmetic logic unit (ALU), reducing the synthesized logic core of processing elements by about 15 % compared to prior flows. Key improvements were also made to the synthesis workflow to better optimize for SiDB logic and incorporate figure-of-merit awareness, which together ensure that the synthesized layouts achieve favorable area scaling and throughput while balancing operational robustness. Evaluations across multiple bit-widths show substantial footprint reductions for configurations within the tractable range of the latest placement-and-routing algorithms while preserving testbench-validated correctness from RTL to dot-accurate SiDB layouts, thereby establishing a reproducible benchmark for EDA on atomic-scale computing. This represents a significant milestone, bridging manually intensive workflows with scalable, automated methodologies, providing a valuable foundation for future design efforts for SiDB-based accelerators.

LLMs increasingly strain memory bandwidth and compute resources as CMOS scaling plateaus. Emerging technologies such as atomic-scale computing with silicon dangling bonds (DBs) promise ultra-dense, low-power logic, yet application-level validation still lacks an executable, clockdriven hardware emulation framework. To address this gap, this work introduces a cross-layer flow that compiles registertransfer level (RTL) Verilog to a clock-driven, Verilator-based emulator exposed to Python via a co-simulation hardware abstraction layer (HAL). DB-aware RTL rules formalized in this work ensure representative emulation across the full systolic array, while allowing the same RTL to drive logic synthesis through fiction, a technology-specific EDA toolkit, to yield dotaccurate DB layouts. As a representative use case, a ternary DB matrix multiply unit (MXU) is designed in Verilog to target BitNet b1.58 acceleration, achieving up to $34 \times$ area reduction compared to prior DB MXUs and generating LLM tokens under cycle-accurate software emulation while matching GPU-baseline outputs. This bridges layout-centric studies and workload-driven evaluation, enabling reproducible, cross-layer accelerator design for this emerging technology.

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology due to its integration density and operating frequency. This advancement is driving the development of comprehensive design automation workflows, including physical simulators and gate design tools. Unlike conventional circuit technology, where logic is implemented through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, standard logic functions like or, and, nand, and so on can be implemented, which are usually provided as standard cells in design processes. However, finding such arrangements that implement a given Boolean function is a tremendously complex task that involves considering numerous candidates and verifying them through computationally expensive physical simulation. Hence, the automatic obtainment of SiDB logic layouts is thus far limited to simple two-input functions only, which already require substantial computation resources. In contrast, conventional physical design algorithms for VLSI have long transitioned from single-gate considerations to multiinput standard cells. To address this challenge, this article proposes QuickCell, a fast algorithm for automatic standard cell design for SiDB logic that uses dedicated search space pruning techniques. In an extensive experimental evaluation, it is demonstrated that combining these pruning techniques yields: 1) a drastic reduction of the search space amounting to up to six orders of magnitude; 2) a corresponding decrease of the runtime by up to a factor of 91; 3) the capability to handle more complex functionality, as, for example, utilized in standard cells, for the first time, significantly narrowing the gap between SiDB logic and conventional CMOS design paradigms; and 4) a significant speedup compared to physical simulation (up to a factor of 10000), with near independence from the number of input-output (I/O) pins when determining the nonoperationality of a given layout. This efficiency makes these techniques-and by extension QuickCell-a powerful enabler for the design of complex standard cells.

Emerging planar computing platforms such as atomic-scale computing and silicon photonics combine gates and interconnects in a single 2D plane, making wiring and crossings dominant bottlenecks. This work reframes differentiable logic network training as one-pass synthesis: BitPlanarNet trains a strictly planar gate network that maps one-to-one to device primitives. Building on differentiable logic gate networks (DL-GNs), each neuron selects a 2-input/2-output primitive and connects only to nearest neighbors, yielding a gate-level layout at discretization. It is demonstrated that this concept is physically viable by successfully fabricating a $33 \times 25 ~\text{nm}^{2}$ representative learned dangling-bond logic layout on a hydrogen-passivated silicon surface using a scanning tunneling microscope. On imageclassification tasks, BitPlanarNet achieves accuracy comparable to unconstrained DLGNs-remaining within approximately 1 percentage point on MNIST and 5 percentage points on CIFAR-10-while guaranteeing planar connectivity, providing a versatile methodology for translating learned tasks directly into realizable gate layouts on emerging planar technologies.

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology. Unlike conventional circuit technology, where logic is realized through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, logic functions can be constructed. However, determining such arrangements is a tremendously complex task. Because of that, the automatic obtainment of SiDB logic implementations is inefficient. To address this challenge, we propose an idea to speed up the design process by utilizing dedicated search space pruning strategies. Initial results show that the combined pruning techniques yield 1) a drastic reduction of the search space, and 2) a corresponding reduction in runtime by up to a factor of 33.

At a time when traditional CMOS technologies approach their fundamental scaling limits and artificial intelligence continues to escalate global computational demands, emerging post-CMOS technologies like Silicon Dangling Bonds (SiDBs) provide promising pathways towards energy-efficient computation. SiDBs offer atomic-scale precision and discrete charge control, enabling the realization of ultra-dense computational logic. However, manual layout design and verification have historically restricted the exploration and scalability of SiDB-based logic systems. To this end, this work demonstrates an automated, end-to-end Electronic Design Automation (EDA) flow for designing and synthesizing a core component of a Matrix Multiply Unit (MXU) from high-level Register-transfer Level (RTL) Verilog descriptions down to dot-accurate SiDB layouts. Leveraging recent advances in SiDB-focused EDA tooling, we demonstrate the first fully automated design flow capable of translating RTL descriptions into manufacturable quantum-dot layouts. The proposed hierarchical Verilog approach addresses existing EDA constraints while facilitating comprehensive operational verification via test benches. Additionally, our design process incorporates reliability-focused Figures Of Merit (FoMs), ensuring the selection of robust logic gates throughout synthesis. Our synthesized MXU Processing Element (PE) layout represents a significant milestone in SiDB logic design, bridging previously manuallyintensive workflows with scalable, automated methodologies. Despite achieving larger footprints than hand-crafted designs, the presented approach provides a valuable foundation for future optimization and widespread adoption of SiDB-based computing architectures.

As Silicon Dangling Bond (SiDB) logic emerges as a promising beyond-CMOS technology, Figures of Merit (FoMs) to assess gate performance become crucial in implementing devices that are robust against environmental variations. Constructing robust SiDB logic involves designing gates that excel across multiple FoMs. However, there exist no clear guidelines on the ideal ranges for FoM values, nor a systematic approach to designing SiDB gates that optimize across multiple FoMs. Motivated by this, this work focuses on addressing the following key objectives: 1) Introduction of a new FoM, called Band Bending Resilience. 2) Determination, presentation, and detailed discussion on the best achievable values for each FoM for all 2-input Boolean functions. 3) Presentation of the versatile cost function chi, unifying multiple FoMs tailored to specific application requirements and priorities. 4) Implementation of the optimization strategy using the cost function chi, which aims at designing SiDB logic with minimal cost, ensuring an optimal balance between all FoMs. Overall, this research contributes significantly to the understanding of SiDB logic, establishing a basis for future progress in the field.

With the impending plateau of Moore's Law, the search for novel computational paradigms has intensified. Silicon dangling bond (SiDB) logic emerges as a promising avenue in this quest, leveraging the quantum-dot-like properties of SiDBs and atomically precise fabrication techniques to realize logic functions at the nanometer scale. Advances in computeraided design (CAD) tools specialized for SiDB logic exploration have also opened the door to novel logic research from the gate- to application-level. This paper introduces a lattice vector formulation for SiDB logic designs on alternative silicon lattice orientations, enabling the exploration of logic gates on arbitrary lattice orientations and addressing the limitations of previous SiDB logic research confined to the H-Si(100)-2 x 1 surface. A comprehensive workflow for designing standard tile libraries compatible with design automation frameworks is proposed, facilitating the scaling of SiDB layouts to large-scale systems implementation on multiple lattice orientations. We demonstrate the proposed lattice vector representation and the library design workflow through a case study on the H-Si(111)-1 x 1 surface, showcasing the first logic gates designed for this orientation. This advancement opens new avenues for SiDB logic research, enabling rigorous evaluations of various lattice orientations for future logic design studies and experimental investigations.

Recent advancements in Silicon Dangling Bond (SiDB) fabrication have transitioned from manual to automated processes. However, sub-nanometer substrate defects remain a significant challenge, thus preventing the fabrication of functional logic. Current design automation techniques lack defect-aware strategies. This paper introduces an idea for a surface defect model based on experimentally verified defects, which can be applied to enhance the robustness of established gate libraries. Additionally, a prototypical automatic placement and routing algorithm is presented, utilizing STM data from physical experiments to obtain dot- accurate circuitry resilient to atomic surface defects. Initial evaluations on surfaces with varying defect rates demonstrate their critical impact, suggesting that fabrication processes must achieve defect rates of around 0.1 % to further advance this circuit technology.

Recent research interest in emerging logic systems based on quantum dots has been sparked by the experimental demonstration of nanometer-scale logic devices composed of atomically sized quantum dots made of silicon dangling bonds (SiDBs), along with the availability of SiQAD, a computer-aided design tool designed for this technology. Latest design automation frameworks have enabled the synthesis of SiDB circuits that reach the size of $\mathbf {32\times 10<^>{3}}\, {\mathbf{nm}}<^>\mathbf {2}$-orders of magnitude more complex than their hand-designed counterparts. However, current SiDB simulation engines do not take defects into account, which is important to consider for these sizable systems. This work proposes a formulation for incorporating fixed-charge simulation into established ground state models to cover an important class of defects that has a non-negligible effect on nearby SiDBs at the $\mathbf {10}\, {\mathbf{nm}}$ scale and beyond. The formulation is validated by implementing it into SiQAD's simulation engine and computationally reproducing experiments on multiple defect types, revealing a high level of accuracy. The new capability is applied towards studying the tolerance of several established logic gates against the introduction of a single nearby defect to establish the corresponding minimum required clearance. These findings are compared against existing metrics to form a foundation for logic robustness studies.

Silicon Dangling Bonds (SiDBs) have emerged as a promising post-CMOS technology for achieving ultra-low power dissipation, establishing themselves as a highly anticipated and environmentally friendly competitor in the realm beyond conventional CMOS. To support the SiDB logic framework, design automation approaches have rapidly evolved. However, at the atomic scale of SiDBs, material imperfections pose a significant roadblock in scaling these devices. Consequently, es-tablished design automation flows, which are defect-agnostic, are inadequate and have not kept pace with the latest experimental findings and advances in fabrication capabilities. A first attempt was recently proposed that extends established defect-agnostic physical design methods by rudimentary defect-aware capabilities. While promising at first glance, in this work, we show that this first attempt yields unsatisfactory results. Subsequently, we present a novel approach that automatically designs a tailored SiDB gate on-the-fly whenever an SiDB gate encounters atomic defects in its vicinity, thereby incorporating these atomic defects into its layout as an integral part. Our experimental evaluations confirm that the proposed approach is capable of designing SiDB circuits of significant complexity and size, even in the presence of atomic defects for the first time. Therefore, this work contributes to advancing this promising post-CMOS technology.

Organic electroactive materials, particularly semiconducting polymers, are at the forefront of emerging organic electronics. Among the plethora of unique features, the possibility to formulate inks out of these materials is particularly promising for the large‐scale manufacturing of electronics at lower cost on a variety of soft substrates. While solution deposition of semiconducting materials is promising for developing printed electronics, the environmental footprint of the materials and related devices needs to be considered to achieve sustainable manufacturing. Towards the development of greener printed electronics, this work investigates the utilization of a non‐toxic, environmentally‐friendly solvent, namely branched polyethylene (BPE), to formulate semiconducting inks. Focusing on a diketopyrrolopyrrole‐based (DPP) semiconducting polymer, shellac as dielectric, and BPE as the solvent, solutions were prepared in different concentrations and their rheological properties were characterized. Then, printing on polyethylene terephthalate (PET) substrates using two different techniques was performed to fabricate organic field‐effect transistors (OFETs). Both printing techniques yielded OFETs with good performance and device characteristics, averaging approximately 10−2 and 10−4 cm2 V−1 s−1, respectively, for slot‐die coating and direct‐ink writing deposition. Notably, despite some difference in threshold voltages, OFETs produced via slot‐die coating and direct‐ink writing showed comparable charge mobilities to previously reported OFETs prepared from similar materials, particularly those prepared on silicon dioxide wafers. Overall, this work confirms the suitability of BPE to formulate semiconducting inks to develop printed electronics in a greener manner. The printing methodology developed in this work also open new avenues for the design of functional printed electronics and related technologies.

Atomically precise manufacturing (APM) is a key technique that involves the direct control of atoms in order to manufacture products or components of products. It has been developed most successfully using scanning probe methods and has received particular attention for developing atom scale electronics with a focus on silicon-based systems. This review captures the development of silicon atom-based electronics and is divided into several sections that will cover characterization and atom manipulation of silicon surfaces with scanning tunneling microscopy and atomic force microscopy, development of silicon dangling bonds as atomic quantum dots, creation of atom scale devices, and the wiring and packaging of those circuits. The review will also cover the advance of silicon dangling bond logic design and the progress of silicon quantum atomic designer (SiQAD) simulators. Finally, an outlook of APM and silicon atom electronics will be provided.

Future remote imaging systems promise spectroscopic functionalities extending well beyond the visible wavelengths. This allows real-time spectral information to be gathered from multiple wavelength bands which is highly attractive for numerous remote sensing spectroscopy/imaging applications and aids target recognition. This paper briefly presents a micro-electromechanical systems (MEMS) based electrically tuneable adaptive filter technology developed for the technologically important infrared (IR) bands of the electromagnetic spectrum and reports on the progress towards extension to the significantly longer wavelength THz band. The demonstrated concepts focus on merging MEMSenabled dynamic modulation with the spectral sensitivity and selectivity of metamaterials, as well as on the possibility of adopting the rapidly evolving 3D printing technologies.

Silicon Dangling Bonds have established themselves as a promising competitor in the field of beyond-CMOS technologies. Their integration density and potential for energy dissipation advantages of several orders of magnitude over conventional circuit technologies sparked the interest of academia and industry alike. While fabrication capabilities advance rapidly and first design automation methodologies have been proposed, physical simulation effectiveness has yet to keep pace. Established algorithms in this domain suffer either from exponential runtime behavior or subpar accuracy levels. In this work, we propose a novel algorithm for the physical simulation of Silicon Dangling Bond systems based on statistical methods that offers both a time-to-solution and an accuracy advantage over the state of the art by more than one order of magnitude and a factor of more than three, respectively, as demonstrated by an exhaustive experimental evaluation.

Silicon Dangling Bonds (SiDBs) constitute a beyond-CMOS computational nanotechnology platform that enables higher integration density and lower power consumption than contemporary CMOS nodes. Recent manufacturing breakthroughs in the domain sparked the interest of academia and industry alike in the race for a green computation future at the nanoscale. However, as the fabrication of SiDBs requires atomic precision, SiDB logic systems are inherently susceptible to environmental defects and material variations, which inevitably occur. The Operational Domain is a methodology to evaluate the resilience of SiDB logic against physical parameter variations. However, state-of-the-art implementations require a quadratic number of exponentially complex physical simulator calls to assess the operational domain. This paper presents two novel algorithms to obtain operational domains in an efficient fashion: one based on flood fill, and one based on contour tracing. Experimental evaluations confirm that they reduce the number of required simulator calls by 70.87% and 95.29 %, respectively. Particularly contour tracing achieves the shift from a quadratic to a linear relation, thereby reducing the complexity and paving the way for realizing reliable SiDB-based computing systems.

As we approach the limit of transistor scaling, an appealing alternative in the form of quantum dots made of silicon dangling bonds (SiDBs) has been experimentally demonstrated to be capable of realizing sub-30 nm 2 logic gates. The introduction of SiQAD, a calibrated computer-aided design tool for the design and simulation of SiDBs, has further enabled the rapid exploration of this novel design space outside of experimental laboratories. Motivated by these advances and by identifying recent demands in machine learning acceleration, this paper proposes an architecture for an SiDB inference accelerator. Area and power estimates are made based on existing logic components and power models, the results are compared against Google's TPUv1. At the same clock rate, the proposed SiDB inference accelerator offers up to 10× improvement in area efficiency and orders of magnitude improvement in power efficiency, showing tremendous promise for further research into this novel platform technology.

Minimally invasive endovascular embolization is used to treat a wide range of diseases in neurology, oncology, and trauma where the vascular morphologies and corresponding hemodynamics vary greatly. Current techniques based on metallic coils, flow diverters, liquid embolics, and suspended microspheres are limited in their ability to address a wide variety of vasculature and can be plagued by complications including distal migration, compaction, and inappropriate vascular remodeling. Further, these endovascular devices currently offer limited therapeutic functions beyond flow control such as drug delivery. Herein, a novel in situ microcatheter‐based photomodulated extrusion approach capable of dynamically tuning the physical and morphological properties of injectable hydrogels, optimizing for local hemodynamic environment and vascular morphology, is proposed and demonstrated. A shear thinning and photoactivated poly(ethylene glycol diacrylate)‐nanosilicate (PEGDA‐nSi) hydrogel is used to demonstrate multiple extrusion modes which are controlled by photokinetics and device configurations. Real‐time photomodulation of injected hydrogel viscosity and modulus is successfully used for embolization in various vasculatures, including high‐flow large vessels and arterial‐to‐arterial capillary shunts. Furthermore, a generalizable therapeutic delivery platform is proposed by demonstrating a core–shell structured extrusion encapsulating doxorubicin to achieve a more sustained release compared to unencapsulated payload.

Although fabrication capabilities of Silicon Dangling Bonds have rapidly advanced from manual labor-driven laboratory work to automated manufacturing in just recent years, sub-nanometer substrate defects still pose a hindrance to production due to the need for atomic precision. In essence, unpassivated or missing surface atoms, contaminants, and structural deformations disturb the fabricated logic or prevent its realization altogether. Moreover, design automation techniques in this domain have not yet adopted any defect-aware behavior to circumvent the present obstacles. In this paper, we derive a surface defect model for design automation from experimentally verified defect types that we apply to identify sensitivities in an established gate library in an effort to generate more robust designs. Furthermore, we present an automatic placement and routing algorithm that considers scanning tunneling microscope data obtained from physical experiments to lay out dot-accurate circuitry that is resilient against the presence of atomic surface defects. This culminates in a holistic evaluation on surface data of varying defect rates that enables us to quantify the severity of such defects. We project that fabrication capabilities must achieve defect rates of around 0.1 %, if charged defects can be completely eliminated, or < 0.1 %, otherwise. This realization sets the pace for future efforts to scale up this promising circuit technology.

Polythiophenes comprise a class of emerging materials with potential applications in the field of temperature sensing. In this article, we validate and apply an integrated blending and printing methodology to combinatorially study libraries of pristine and compositionally graded blends of polythiophenes PEDOT:PSS and P(S-EDOT) (a PEDOT-like self-doped conjugated polymer) to understand their intrinsic electrical conductivity behaviour and along with its temperature dependence on blend composition and ambient temperature. Hypothesis testing is conducted to identify optima in electrical conductivity from combinations of input material proportions intended to meet multiple requirements otherwise difficult to achieve in any single-component solution-processable material. We chose PEDOT:PSS as a commercial developed intrinsically conductive polythiophene and with it, compared a novel self-doped polythiophene P(S-EDOT) as its potential replacement or complement as a sensor material. The electrical and morphological characteristics for both polymers and their blends were investigated for use as different components of temperature sensing applications. Different error sources within the process flow were considered for statistically significant conclusions regarding the utility of different compositions for different aspects of temperature sensing.