Supporting advanced modulation schemes such as 16 quadrature-amplitude modulation (QAM) in a high-speed transimpedance amplifier (TIA) requires minimizing noise and total harmonic distortion (THD) across gain settings and frequency. Accordingly, our automatically reconfigurable TIA reduces base resistor noise, gain peaking, phase margin (PM) degradation, and $f_{T}$ degradation, operating on a single sense voltage and eliminating the need for multiple control loops. A collaborative offset and dc current cancellation technique is introduced to reduce offset-induced nonlinearity, while protecting the receiver (RX) against current overdrive. A prototype of the RX is fabricated on 130-nm SiGe BiCMOS process and demonstrates a maximum gain of 75.5 dB $\Omega $ with 35.5 dB of dynamic range, 42-GHz bandwidth (BW), and a maximum gain averaged input-referred noise (IRN) of 18.5 pA/ $\sqrt {\text {Hz}}$ . The silicon-photonic transceiver assembly incorporating four such RXs achieves 25-dB required optical signal to noise ratio (ROSNR) for received optical power between–22 and 1 dBm at 50 Gbaud, and aggregate data rate of 528 Gb/s/ $\lambda$ at 66 Gbaud and 25-dB ROSNR.

Traditionally, the high-performance optical coherent communication TX has been a discrete assembly based on LiNbO3 modulators and III-V drivers. While delivering high bandwidth (BW) and linearity, such a platform is bulky and does not work for high-volume or intra-datacenter applications. Silicon photonics (SiPh) offers a Si-based platform for next-generation transceivers by integrating all required optical functions. But even in existing SiPH-based commercial modules, the driver generally remains a III-V-based chipset, impeding the path to an all-silicon solution. The challenge for an all-silicon-based coherent optical TX is in the simultaneous requirement of high differential voltage swing (Vppd), linearity and BW. In this work, we present a 130nmSiGe driver achieving a 6Vppd swing, 3.6% THD and small-signal BW over 40GHz. Co-packaged with a SiPh transceiver, the driver enables the same level of performance as LiNbO3 modulators with III-V drivers and demonstrates 272Gb/s dual-polarization (DP)-160AM transmission. This is enabled using (1) circuit techniques that achieve a BW extension ratio (BWER) of $4.5\times $ for the Mach-Zehnder modulator (MZM) driver while simultaneously achieving large swing ($\mathrm {V}_{\mathrm {p}\mathrm {p}\mathrm {d}}$=6V), high linearity (THD $=3.6$%) and mitigating breakdown voltage (BV) and reliability concerns with large Vppd; (2) pre-emphasis control in the driver output stage and gain control in the pre-driver VGA to compensate for the electro-optic (E/0) BW of the TX over corners; and (3) a monolithic integration of MZMs with a polarization rotator (PR) optimized for high-BW, low-crosstalk and co-integration with drivers for DP-OAM and DP-OPSK operation.

We present a co-designed silicon traveling wave modulator with a SiGe driver with 6Vpp effective swing. 34GBaud DP-16QAM is demonstrated with comparable ROSNR performance to a commercial CFP2-ACO.

A wide-swing optical modulator driver is implemented in 0.13-mu m SiGe-BiCMOS using a three-stage distributed amplifier with a digital input line. Measurements demonstrate 6-Vp-p differential output, symmetric 6-ps (min) rise/fall times, 333-fs (rms) additive jitter, and better than 20-dB output return loss (S-11) below 58 GHz. Full output swing with adjustable (6-12 ps) rise/fall times is realized after a three-step calibration sequence facilitated by an on-chip energy detector and digital control. The circuit supports 28-48-Gb/s external data sources, or 2(11) -1 PRBS and 1-0 internal data generators for calibration and characterization respectively. The 3-mm(2) driver IC (1.8-mm(2) active area) consumes 1.92 W from + 5/-2.5-V supplies.

Presents corrections to the paper, “A DC-100 GHz active frequency doubler with a low-voltage multiplier core,” (Vera, L. and Long, J.R.) IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 1963–1973, Sep. 2015.

A 211-1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 are distributed via the synthetic lines to optimize power-speed tradeoffs in the design. The 790 × 620 μm2 PRBS designed in 130-nm SiGe BiCMOS (200/280 GHz fT/fmax) consumes 250 mA at 2.5 V (i.e., 625 mW).

Cross-coupled differential pairs implement an even-order active frequency multiplier in 90 nm SiGe-BiCMOS. The multiplier core uses asymmetric biasing to realize an even-order transfer function. Wideband (WB) and narrowband doublers built around the active core are proposed, and their relative performance is compared from simulation. Measurement of a WB prototype consisting of the doubler, active load with feedback regulation of bias, and 50 Ω input and output buffers validates the circuit concepts. Conversion gain (CG) for the WB doubler peaks at low frequency (e.g., 12 dB at 10 GHz) and rolls off to 0 dB at 100 GHz. For 25 GHz output, significant spurs are: -25 dBc at 12.5 GHz (input tone) and -28 dBc at 50 GHz (4th harmonic). The 0.37 mm 2 WB testchip consumes 55.5 mA from a 4.5 V supply.

A dual-mode dynamic/static (dynastat) divided-by-two combines the range of a static frequency divider (DC-117 GHz from simulation) and the higher toggle frequency of a dynamic divider (85–153 GHz, simulated) at a low input sensitivity of 0.2 Vpk differential (<−3 dBm into 50 Ω). The measured self-oscillation frequencies of the prototype are 79 GHz (static) and 129 GHz in dynamic mode. The 8880 μm2 dynastat implemented in 90 nm silicon germanium (SiGe)-bipolar CMOS consumes 38 mA (static) and 19 mA (in dynamic mode) from a 4.5 V supply.

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBM's large volume 200mm fabrication line. The technology features 300 GHz fT and 360 GHz fMAX high performance SiGe HBTs, 135 GHz fT and 2.5V BVCEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

A broadband, active doubler based on asymmetrically biased differential pairs delivers conversion gain (CG) from DC to 100 GHz. Measured CG is >10 dB up to 50 GHz, >6 dB up to 80 GHz, and >0 dB up to 100 GHz. Second-harmonic (4× the input) suppression is -28 dBc at 50 GHz. Implemented in a 90 nm SiGe technology, the 0.371 mm2 multiplier core consumes 25 mA from a 4.5 V supply.

A 10 Gb/s, digitally controlled, differential distributed amplifier (DA) optical modulator driver is implemented in 0.18 mu m SiGe-BiCMOS technology. The 2.87 mm(2) prototype integrates clock phase shifters, digital latches, limiting amplifiers, broadband n+/n-well back termination resistors and a substrate-shielded output line on chip. It produces 6 Vp-p differential output swing across 50 Omega loads. The output edge speed is trimmable, with 20-80% rise/fall times ranging from < 15 ps to 50 ps at 10 Gb/s. Minimum sensitivity of the ECL-compatible inputs is 65 mV(p-p) at 10 Gb/s single-ended, with negligible additive jitter. Measured output return loss is better than 10 dB below 35 GHz, sufficient to drive an external push-pull Mach-Zehnder optical modulator. Total power consumption is 2.13 W operating from -5.2 V and 5 V supplies. The fully-digital input interface supports scalability in the number of DA stages, output swing and to multiple output channels.

The bandwidth of a single-stage, SiGe-HBT Darlington amplifier with feedback is improved 53% by cascoding and series peaking at the input, and by 25% for peaking alone. The cascode amplifier realizes 12-dB gain and better than 110GHz bandwidth (123GHz from simulation). Measured |S11| and |S22| are >10dB, group delay is ~6ps, and GBW/Pdc is 9.1GHz/mW. The 0.003mm2 amplifier core is implemented in 90nm SiGe-BiCMOS and consumes 48mW from a 2.1V supply.

This paper describes a 10Gb/s, digitally-controlled distributed amplifier (DA) implemented in 0.18μm SiGe (60GHz peak-fT) with 6Vpp differential output swing, <;20ps symmetric rise/fall times, negligible additive jitter and >10dB return loss across 30GHz bandwidth; performance suitable for driving a dual (i.e., balanced) MZ modulator. Unlike conventional DAs, which use a passive transmission line at the input to feed each amplifier cell with the correct signal phase, the gain cells in the prototype modulator driver are driven by digital latches. The fully-digital interface at the DA input leads to a scalable design by eliminating the performance impairments of the input transmission line.

Silicon SoCs capable of millimeter-wave frequency operation now offer a combination of performance, functionality, integration scale and cost unrivalled by other IC technologies. The components, design techniques and circuits that are propelling deep submicron silicon technologies in mm-wave system front-ends are surveyed in this paper. Examples relevant to Gbit/s rate wireless communication are highlighted, with emphasis on innovations drawn from the recent literature.