A phase shifter based on GaN/AlxGa1-xN superlattice is experimentally evaluated, achieving a phase-shift efficiency of 7.2V·cm at 1550 nm. The phase-shifter relies on a SiN-rich rib waveguide with a 13

A new simultaneous acquisition software for Precession Electron Diffraction (PED) and Energy Dispersive X-ray Spectroscopy (EDX) mapping has been developed. This approach has been used to study the RESET operation in Ge-rich Ge-Sb-Te (Ge-rich GST) non-volatile Phase-Change Memory (PCM). Such an operation consists in the local amorphization of the device's active volume, which defines the memory state. Using PED patterns indexing, we were able to segment the amorphous area, and access its composition through EDX quantification. Moreover, both the spatial distribution and the chemical composition of the two crystalline phases overlapped in the chalcogenide layer were retrieved by using the spectral unmixing approach and PED patterns indexing. It evidences that Ge and Ge2Sb1Te2 (GST-212) crystals are separated in the studied devices. Despite this, we show that Ge-enrichment is preserved in the active volume of a functional device, which is crucial to guarantee the RESET state stability at high temperature. We also link the origin of the failure of the RESET operation observed in a dysfunctional device to the larger Ge-depleted area.

In this work, heated implantation impact on defect generation is observed for non-amorphizing conditions and specific anneal. Photoluminescence imaging method has been used and exhibits radiative defect density variation with chuck temperature. Moreover, to understand the behavior of such implantation in terms of defect generation and depth profile, effectiveness of Kinetic Monte Carlo (KMC) simulations is discussed.

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

Two types of industrial transistor technologies have been studied using atom probe tomography (APT). Both 14 nm node high-K metal-oxide-semiconductor field effect transistors (MOSFETs) on ultrathin body and buried oxide and 320 GHz Ft Si/SiGe Heterojunction Bipolar Transistors (HBT) embedded in a 55-nm BiCMOS chip have been analysed and their atomic distribution has been mapped. Due to the limitations of routine characterisation techniques, boron can remain invisible in such nanometric sized structures. Also, size effects can induce differences between the actual device and larger test zones used for monitoring these technologies. This paper presents results obtained by APT from two advanced nodes, in contrast to complementary techniques. Using different methodologies, including specific APT-friendly test structures and multiple-impact data filtering, the dopant behaviour in these structures can be better understood. An unexpected boron distribution in both the MOSFET source/drain and HBT base regions has been highlighted. Published by AIP Publishing.

Journal Article A Comparative Analysis of a Si/SiGe Heterojunction-Bipolar Transistors: APT, STEM-EDX and ToF-SIMS Get access Robert Estivill, Robert Estivill STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, FranceUniv. Grenoble Alpes, F-38000 Grenoble, France CEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceGroupe de Physique des Materiaux - GPM UMR CNRS 6634, Universite de Rouen, France Search for other works by this author on: Oxford Academic Google Scholar Pascal Chevalier, Pascal Chevalier STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Search for other works by this author on: Oxford Academic Google Scholar Frederic Lorut, Frederic Lorut STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Search for other works by this author on: Oxford Academic Google Scholar Marc Juhel, Marc Juhel STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Search for other works by this author on: Oxford Academic Google Scholar Laurent Clement, Laurent Clement STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Search for other works by this author on: Oxford Academic Google Scholar Germain Servanton, Germain Servanton STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Search for other works by this author on: Oxford Academic Google Scholar Gregory Avenier, Gregory Avenier STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Search for other works by this author on: Oxford Academic Google Scholar Adeline Grenier, Adeline Grenier Univ. Grenoble Alpes, F-38000 Grenoble, France CEA, LETI, MINATEC Campus, F-38054 Grenoble, France Search for other works by this author on: Oxford Academic Google Scholar Didier Blavette Didier Blavette Groupe de Physique des Materiaux - GPM UMR CNRS 6634, Universite de Rouen, France Search for other works by this author on: Oxford Academic Google Scholar Microscopy and Microanalysis, Volume 21, Issue S3, 1 August 2015, Pages 689–690, https://doi.org/10.1017/S1431927615004249 Published: 23 September 2015

The authors have measured and compared the stress in nickel silicide full sheet layers prepared with added platinum on (001) p-type Si wafers by using either a rapid thermal anneal (RTA) at 390 °C or a millisecond submelt laser dynamic scanning anneal (DSA) at 800 °C. The room temperature tensile stress of the silicide annealed with DSA is 1.65 GPa, whereas that of the silicide annealed with RTA at 390 °C is 800 MPa. Our analysis confirms that the origin of the stress lies in thermal expansion factors. Despite some small variations, the stress remains highly tensile in both layers after a 1 h post-treatment at 400 °C, with values of 1.4 GPa and 850 MPa for the DSA and RTA samples, respectively. The authors also performed strain measurements with dark field electron holography in the source drain region of 28 nm field complementary metal oxide semiconductor field effect transistors, under the silicide dot. They then determined the stress inside the silicide by combining the strain measurement with finite element mechanical simulations; values of 1.5 GPa and 600 MPa were found at the nanometer scale for the DSA and RTA samples, respectively, which are consistent with the macroscopic observations.

In this article, we propose to use Electron Backscattered Diffraction (EBSD) to characterize microstructure of copper interconnects of thin metal level in top view and cross view. These two views give very complementary information about microstructure of copper and thus about recrystallization of copper during annealing. Moreover, for minimum width, as interconnect is two times thicker than wide; It will be easier to analyze smaller interconnect of 45 nm node technology in cross‐section. We look for evolution of texture and microstructure of copper with line width in top view and in cross view. We highlight the presence of two recrystallization mechanisms and also the fact that transition from one to the other is progressive with competition of both mechanisms.

Extended abstract of a paper presented at Microscopy and Microanalysis 2004 in Savannah, Georgia, USA, August 1–5, 2004.