This article presents the analysis of selected maximum power point tracking (MPPT) algorithms and their influence on developed energy harvester (EH) systems under uniform conditions. The energy harvester is an electronic system that converts available ambient energy to electrical energy and regulates its distribution to the output. The aim is to design an energy harvester with the highest integration rate possible with consideration of area requirements and low power consumption. To improve the overall energy conversion of the developed harvester, we implemented several MPPT algorithms (Pilot Cell, Constant Voltage, Perturb and Observe) into a dedicated MPPT controller that controls the DC-DC converter. Consequently, we experimentally analyzed their impact on the harvester system. Findings show that even simple algorithms with smaller chip areas and lower power consumption can achieve results comparable to more complex ones. The proposed, manufactured and experimentally evaluated EH chip prototype has proven its expected functionality and is therefore fully capable of supplying energy for low-power electronics and battery-operated devices.

This article introduces the design and analysis of a slope detection circuit tailored for on-chip sensing of the load current in DC-DC converters. The novel indirect sensing approach is grounded in measuring the output voltage slope across the filtering capacitor during discharge phases. Consequently, this slope data can be effectively harnessed to control the converter switches. The slope detector circuit was designed in standard 65 nm CMOS technology using the nominal supply voltage of 1.2 V and can be used for current sensing within the range from one to hundreds of mA. Since the proposed circuit has mainly digital character, the robustness to process, temperature and supply voltage variations can be ensured rather conveniently.

This paper proposes an analysis of digital method of input offset compensation in operational amplifier, integrated as a single system in 130 nm CMOS technology. The whole system of digitally calibrated amplifier operates with 0.6 V supply voltage and consumes less than 80 mu W of power. The paper includes small-signal analysis investigating possible adverse effects of added calibration hardware on the calibrated amplifier. Proposed solution was verified through Monte Carlo simulations in temperature range from -20 degrees C to 85 degrees C in Cadence design environment. Using the proposed method of calibration, the input offset voltage of operational amplifier was suppressed from 278 mu V to 22 mu V (in terms of mean value).

This paper addresses the design and verification of a voltage comparator of novel topology, implemented in a 65 nm general-purpose CMOS technology. The proposed circuit combines a bulk-driven transistor approach with so-called currentmode operation, which enables truely promising ultra-low-voltage performance. Design verification has been carried out using Monte-Carlo simulations across an industrial temperature range from $T=-20^{\circ} C$ to $T=85^{\circ} C$, as well as through simulations across all relevant process-voltage-temperature (PVT) corners. The proposed topology demonstrates the ability to operate correctly with $V_{D D}$ as low as 250 mV with rail-to-rail input voltage range. The comparator can achieve a very low input offset voltage without trimming or digital calibration, at the cost of increased silicon area consumption. However, the presented topology can be easily modified to implement various trimming methods, if required.

The article outlines the DSP (digital signal processing) hardware design essentials required for designing any complex systems such as neural networks or AI in general. Initially, two mostly used numerical data representations for storing rational (fractional) binary values are explained, followed by their practical use and properties demonstration in HDL (hardware description language) design of low-power reconfigurable FIR (finite impulse response) filter for nano-scale CMOS technology, as the FIR filter structure is closely related to that of a neuron. Finally, the most crucial part of the design process is portrayed: the thorough testing by developed application enabling user-friendly interaction with the FIR filter.

This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-user is then capable of changing the number of active coefficients (filter order) and their value. All flip-flops can be rearranged into 1-bit scan-chain for production test, and it can also be used for filter debugging. MATLAB application was developed for easier interaction with the FIR filter. It allows the user to set the coefficients, process the samples, scan and display the contents of flip-flops.

The paper addresses an ongoing research in the field of ultra low-power and ultra low-voltage IC design and compact modelling of MOS transistors in nanoscale CMOS technologies. We discuss the current state-of-the-art of analog bulk-driven integrated circuit (BD IC) design in modern sub-l00 nm CMOS processes, and we also discuss the obvious need for accurate MOS device modelling in such operating conditions. Based on our initial research carried out mainly using 130 nm CMOS, we decided to migrate to 65 nm CMOS process. Naturally, this introduces a whole new level of difficulties for analog designers, as well as for developers of bulk-driven simulation models. We describe the development and application of EKV3.0 transistor model in ultra low-voltage / low-power analog bulk-driven IC design in 65 nm CMOS process.

This article presents measurement circuits and a test board developed for the experimental evaluation of prototype chip samples of the Fully Differential Difference Amplifier (FDDA). The Device Under Test (DUT) is an ultra low-voltage, high performance integrated FDDA designed and fabricated in 130nm CMOS technology. The power supply voltage of the FDDA is 400mV. The measurement circuits were implemented on the test board with the fabricated FDDA chip to evaluate its main parameters and properties. In this work, we focus on evaluation of the following parameters: the input offset voltage, the common-mode rejection ratio, and the power supply rejection ratio. The test board was developed and verified. The test board error was measured to be 38.73mV. The offset voltage of the FDDA was −0.66mV. The measured FDDA gain and gain bandwidth were 48dB and 550kHz, respectively. In addition to the measurement board, a graphical user interface was also developed to simplify the control of the device under test during measurements.

The publication is primarily written for students of the first year at FEI STU in Bratislava. It is focused on subject Logical Systems for programs Applied Informatics, Electronics, Robotics and Cybernetics and Information and Communication Technologies. The publication presents a solved problems for lectures and seminars from a subject Logical Systems. The text is formally written so it covers the whole subject during the first semester.

The paper discusses an analog voltage comparator designed in general purpose 65 nm CMOS technology, capable of processing the input signal in rail-to-rail range thanks to its novel circuit topology. The main assets of the proposed comparator are the ability of working in ultra low-power, as well as ultra low-voltage conditions, its minimized input offset voltage without the need of calibration or post-process trimming, industrial temperature range (−20 °C to 85 ° C) and an absence of internal biasing circuitry. Additional features include the enable function and hysteresis, which can be turned on and off by input digital signal. The design's robustness and accuracy has been extensively verified in all relevant process and temperature corners, using post-layout extracted netlist, as well as Monte-Carlo analysis simulating random process variations and mismatch between the components. The worst-case power consumption of the proposed comparator design remains safely below 1 $\mu \mathbf{W}$ , while in nominal conditions, it does not exceed the first third of nano-watt range. Although, further power reduction can be achieved by lowering the supply voltage, as the topology allows for $V_{DDmin}$ below 250 mV at room temperature.

The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard “gate-driven” (GD) control of MOS transistors and is designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional “bulk-driven” (BD) control of active devices in the circuit. Each presented circuit topology has its own pros and cons. However, both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, wide temperature range (from −20 °C to 85 °C) and for random process variations as well. Both presented comparator designs can reliably operate with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on chip prototypes.

The paper addresses a re-design and parameter analysis of a current-mode rail-to-rail voltage comparator with power consumption in nano-watt range across all PVT corners. The comparator design was done in general-purpose 65 nm CMOS technology with the nominal power supply voltage of 1.2 V. The circuit design needs to function properly in industrial temperature range, which is from -20°C to 85°C. The rail-to-rail input voltage range is achieved without employing two differential pairs and also without an internal voltage biasing circuitry. Furthermore, the design process can be easily automated by means of calculation spreadsheet and employing $g_{m}/I_{D}$ design methodology. The presented comparator has been analyzed for robustness and accuracy across all PVT corners using post-layout extracted netlist. A number of parameters was investigated by Monte-Carlo analysis. The power consumption does not exceed $\mathbf{1}\ \mu \mathbf{W}$ in the worst-case scenario, however in typical conditions, it remains below the first third of nano-watt range. The circuit also contains enable signal to minimize the power consumption when the circuit's function is not required. The topology itself, exhibits a promising potential for further research, since it can also work in ultra low-voltage regime thanks to only two stacked transistors.

The paper describes design and analysis of a Low-Dropout Regulator (LDO) with a high value of the power supply rejection (PSR) at high frequencies (above 10MHz). The proposed LDO was designed in a standard 65 nm CMOS technology. The output of the designed LDO can be adjusted by the voltage reference used in the LDO. The obtained results prove a very good PSR parameter at frequencies above 10 MHz, where the value of -40 dB is observed in the worst case. Additionally, the designed LDO topology exhibits promising load regulation properties even for a low value of the output capacitor. The proposed LDO can be fully integrated on a chip, and used in complex switching converter Systems on-Chip (SoC), where a high value of PSR is required.

The paper addresses a novel comparator topology capable of processing the input signal in rail-to-rail range, designed in standard general purpose twin-well nanoscale CMOS technology without two differential input pairs. The power supply voltage of 1.2 V was used and the operating temperature span was set to a standard industrial limits (from −20 °C up to 85 °C). Its application is aimed to low-power energy harvesting circuit, therefore its current consumption has been minimized as much as possible, since it stands out as a crucial parameter. The presented topology operates in so-called current-mode and represents a gate-driven version of already published topology, which was described in deep detail in [1]. The designed comparator has been verified for robustness and accuracy across all process and temperature corners, as well as by the Monte-Carlo analyses. Its power consumption does not exceed $1.05\ \mu\mathrm{W}$ in worst-case scenario, while in the nominal conditions, the value remains safely in the first half of nW range. The topology also shows great potential for low-voltage applications, as well since it employs only two stacked transistors.

The paper addresses a development and application of EKV MOS transistor compact model with focus on the ultra low-voltage / ultra low-power analog integrated circuit (IC) design employing bulk-driven (BD) technique. The presented contribution can be viewed as an extension of standard EKV model application and as a contribution to ultra low-voltage IC design techniques. The paper compares the measu...

The paper addresses a development and application of EKV MOS transistor compact model with focus on the ultra low-voltage / ultra low-power analog integrated circuit (IC) design employing bulk-driven (BD) technique. The presented contribution can be viewed as an extension of standard EKV model application and as a contribution to ultra low-voltage IC design techniques. The paper compares the measured and extracted small-signal parameters of standalone transistor samples fabricated in 130 nm CMOS technology and the simulation results obtained using the proposed bulk-driven EKV v2.63 model and foundry-provided BSIM model v3.3. The transistor samples were analyzed with power supply of VDD = 0.4 V The paper also discusses the implementation of 3D graphs as a result of introducing another degree of freedom into the essential MOS transistor characteristics, while maintaining the ease of using the design hand-calculation with the original g m /ID approach.

The paper is focused on the design and analysis of a fully on-chip Low-Drop Regulator (LDO) that was implemented in 130 nm CMOS technology. The proposed LDO was designed using the low-voltage technique in order to achieve reliable work in the wide input voltage range. The output voltage of the proposed LDO was set to 0.4 V while the maximum input voltage value of 1.2 V was used. The achieved results shows very good line and load regulation as well as high voltage conversion efficiency under the above-mentioned supply voltage conditions. The presented LDO has been used in a complex ultra-low voltage system that is fully integrated on a chip.

The paper addresses a development and evaluation of well-known EKV MOS transistor model with focus on the ultra low-voltage / ultra low-power analog IC design employing rather "exotic" bulk-driven technique. The presented contribution can be viewed as an extension of already established compact simulation model with modifications to the original parameter extraction flow. The article contains a brief description of EKV model fundamentals, a novel parameter extraction flow and most importantly, the comparison of developed EKV model with the foundry-provided BSIM model (v3.3) and the experimental measurement data obtained from prototype chip samples fabricated in 130 nm CMOS technology.

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600mV with 10% variation, in temperature range from −20°C to 85°C. Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13μV to 167μV. With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.

The power saving issue and clean energy harvesting for wireless and cost-affordable electronics (e.g., IoT applications, sensor nodes or medical implants), have recently become attractive research topics. With this in mind, the paper addresses one of the most important parts of the energy conversion system chain – the power management unit. The core of such a unit will be formed by an inductorless, low-voltage DC-DC converter based on the cross-coupled dynamic-threshold charge pump topology. The charge pump utilizes a power-efficient ON/OFF regulation feedback loop, specially designed for strict low-voltage start-up conditions by a driver booster. Taken together, they serve as the masters to control the charge pump output (up to 600 mV), depending on the voltage value produced by a renewable energy source available in the environment. The low-power feature is also ensured by a careful design of the hysteresis-based bulk-driven comparator and fully integrated switched-capacitor voltage divider, omitting the static power consumption. The presented converter can also employ the on-chip RF-based energy harvester for use in a wireless power transfer system.