This work investigates the reliability of AlScN/GaN High-Electron-Mobility Transistors (HEMTs) by integrating experimental analyzes with Technology Computer-Aided Design (TCAD) simulations. The study focuses on pulsed I-V measurements and High-Temperature Reverse Bias (HTRB) step-stress tests. The former have been performed under different quiescent conditions highlight short-term transient charge trapping, while the latter reveals long-term threshold voltage (V-th), transconductance (gm), saturation drain current (I-D,I-ss) and gate leakage (I-G) shifts. A TCAD model calibrated on experiments is employed to deeply understand the interplay of the different sources of degradation. In pulsed analyzes, iron traps are identified as the primary degradation contributors. In HTRB step-stress regime, trapped charges under the gate at the 2DEG interface are modeled to reproduce the V-th shift, while the decreased gm is mostly ascribed to donor-trap detrapping at the SiN passivation interface. The relative OID,ss[%] shift and I-G are used to validate the proposed approach. Such insights also provide a net comparison of the degradation phenomena in AlScN-based HEMTs with respect to AlGaN-based counterparts, paving the way for improved technology and device designs.

This work reports on the fabrication of vertical GaN FinFETs on a sapphire substrate. The FinFET concept allows for realizing normally-off transistors with dense multi-channel structures. However, using time-consuming e-beam lithography represents an obstacle to effective device production at a wafer level. Therefore, this work investigates the possibility of creating thin fins at submicrometer dimensions below a width of 200 nm using i-line lithography. Starting with broad fins and thinning them with a wet etch resulted in an undesired shortening of the length of the fins, necessitating structuring the fins with widths significantly below the used wavelength. Our process proves capable of achieving fin widths in the range of 100 nm. The FinFETs consist of at least 100 fins and exhibit a maximum averaged threshold voltage (V-th) of (0.90 +/- 0.10) V. V-th displays the expected parabolic decrease with increasing fin width, becoming negative at around 400 nm. The contributions of the accumulation channel and the bulk fin are distinguished in the transconductance profile. Small-signal RF characterization of a device featuring a fin width of 370 nm shows maximum values of f(t) = 3.3 GHz and f(max) = 5.2 GHz.

This work investigates the thermal characteristics of gallium nitride (GaN) high-electron mobility transistors (HEMTs) for power applications. Exemplarily, a 650-V class HEMT is analyzed by different thermal characterization methods such as transient I-V measurements, infrared (IR) microscopy, and simulations, presenting a comprehensive insight into the thermal behavior. A new electrothermal model function is derived for the extraction of thermal parameters by transient I-V measurements, and it is not limited to the linear region of the output characteristic, as a model presented in previous work, but also applicable in the saturation region. Fifth-order Foster model parameters are extracted for different operating points in linear and saturation regions. For verification and better understanding, the measurements are also performed by IR microscopy at same operating points enabling the characterization of the device's surface temperature distribution. Two new analytical models allow the interpretation of the temperature distribution and are used as fit formulas for extracting the thermal parameters found by IR microscopy. Finally, the research includes an investigation using technology computer-aided design (TCAD) simulation, followed by a thermal 3-D finite element simulation. The results allow a deeper understanding of the electrothermal behavior of GaN power HEMTs at various operating points.

The long-term reliability of AlGaN/GaN high electron mobility transistors (HEMTs) is a crucial factor in their widespread adoption for high-power and high-frequency applications. Before investigating the device behavior under high-temperature reverse-bias (HTRB) conditions, a fine tuning of the TCAD simulation setup was conducted by benchmarking against measured transfer, input, and output characteristics. This calibration step ensured an accurate representation of the device electrical performance, serving as a solid foundation for further TCAD stress analysis. Subsequently, the comparison between HTRB experimental results and the calibrated TCAD simulations was carried out to understand degradation mechanisms under stress conditions. The study particularly focuses on the role of passivation/cap interface traps, which are known to influence both the drain current (ID) and gate current (IG) over time. By varying key parameters such as trap density and energy levels, the impact of these traps on device performance is consistently explored. The simulations not only corroborate experimental findings but also provide deeper insights into the physical mechanisms driving current collapse, enabling more accurate predictions of long-term device behavior under high-stress conditions. These results contribute to the ongoing development of more reliable GaN-based technologies, emphasizing the importance of interface quality and trap management.

We report on the development of the co-integration of a common lateral HEMT (high-electron mobility transistor) technology with vertical GaN devices based on a CAVET (current aperture vertical electron transistor) design on the same chip/die. Process and device design parameters are discussed and optimized. Large-area vertical devices with drain-currents/breakdown-voltages of up to 20 A/250 V and lateral devices with breakdown voltages VDS > 30 V are demonstrated on the same die and subsequently diced and packaged. Finally, multi-pulse tests in a double pulse test setup (inductive load) are demonstrated with lateral HEMTs as a gate-driver stage and a vertical CAVET with maximum drain current >4 A at 250 kHz and VIN = 40 V on a total chip area of 3 mm 2 , This work demonstrates a technology platform for a direct integration of vertical GaN power devices with lateral functionality.

The fin field-effect transistor (FinFET) is a promising candidate among vertical GaN-based transistors as it is inherently unipolar and requires neither p-type doping nor regrowth processes [1 , 2] . While commonly regarded as a high power device, recent research has started to explore its potential as a high frequency transistor [3 , 4] . In our previous work, we demonstrated a small-signal current gain of f t = 10.2GHz for a FinFET with 20 fins [4] . More recently, we presented our investigations on the scaling of the fin length and its influence on the small-signal performance based on FinFETs processed on 3 inch sapphire substrate [5] . In this work, we expand our studies to investigate the scaling effect of the number of fins in FinFETs, and report new record values for the maximum frequency of oscillation f max for vertical GaN transistors.

In this paper, we outline the current state of the art and trends for future development in millimeter-wave (mmw) amplifiers based on gallium nitride (GaN) semiconductors. To that end, we give an overview of recent technological results of currently operational GaN foundries and classify them with respect to their maximum frequency of operation and the current-gain cutoff frequency. Furthermore, focusing on frequencies above 80 GHz, we develop a comprehensive survey of GaN high-power amplifiers (HPAs) and provide a comparison to competing technologies such as indium phosphide (InP) and silicon germanium (SiGe). We also introduce a newly developed 6-stage GaN amplifier that is targeted towards the upper D-band. It provides an output power of up to 22.0 dBm, which sets a new record for GaN HPAs in this band. From our survey, we find that while GaN exhibits an impressive power density, its gain and efficiency characteristics particularly beyond 120 GHz still warrant improvement. Therefore, we describe several areas of future improvement such as the gate module scaling, mitigation of trapping phenomena and recent trends in processing of ohmic contacts and alternative epitaxial stacks. With these further developments, more widespread adoption of GaN-based technologies at even higher frequencies seems feasible in the coming years.

The reliability issues of AlGaN/GaN high electron mobility transistors (HEMTs) are investigated through technology computer-aided design (TCAD) simulations in order to predict, for the first time, on-wafer stress measurements monitored in the step-stress high-temperature reverse-bias (HTRB) tests and correlate them to the pulsed DC I-V characteristics under zero bias, cold and hot pinch-off. First, the calibration of the TCAD setup is addressed with special focus on the adopted physical models together with the definition of the different trap concentrations. Second, the pulsed DC characteristics are simulated to assess the relevant parameter sensitivities and validate the TCAD approach against experiments at different stress conditions. Third, the HTRB stress is studied in order to evaluate the main features affecting the device when subjected to high voltage and high temperature operations. Results indicated that the main parameters involved in current collapse are donor traps at the passivation/cap interface and the Fe-related acceptor traps given by the doping diffusion in the channel region. The latter affects the pulsed performance, while totally recover in the HTRB regime. Vice versa the partial discharge of the donor traps at the interface plays a key role in the HTRB degradation.

Among the vertical GaN transistors, the FinFET is an unipolar device which therefore neither needs p-type doping nor regrowth processes [1]. Large area devices with currents of several amperes and high breakdown voltages beyond 1 kV were presented [2], [3]. So far, the FinFET has been investigated as high-power device and only little interest has been given to his potential as high-frequency transistor [4], [5]. Although normally-off FinFETs were realized on expensive bulk GaN substrates, the sole normally-off FinFET on foreign substrate relied on an introduction of p-GaN, thereby relinquishing the unipolar nature of the FinFET and suffering from the low mobility in the p-channel [6]. In this work, we demonstrate the first normally-off quasi-vertical FinFET on SiC substrate with an analysis of its small-signal performance.

The reliability issues of AlGaN/GaN high electron mobility transistors (HEMTs) are investigated through technology computer-aided design (TCAD) simulations in order to predict, for the first time, on-wafer stress measurements monitored in the step-stress high-temperature reverse-bias (HTRB) tests and correlate them to the pulsed DC I-V characteristics under zero bias, cold and hot pinch-off. First, the calibration of the TCAD setup is addressed with special focus on the adopted physical models together with the definition of the different trap concentrations. Second, the pulsed DC characteristics are simulated to assess the relevant parameter sensitivities and validate the TCAD approach against experiments at different stress conditions. Third, the HTRB stress is studied in order to evaluate the main features affecting the device when subjected to high voltage and high temperature operations. Results indicated that the main parameters involved in current collapse are donor traps at the passivation/cap interface and the Fe-related acceptor traps given by the doping diffusion in the channel region. The latter affects the pulsed performance, while totally recover in the HTRB regime. Vice versa the partial discharge of the donor traps at the interface plays a key role in the HTRB degradation.

Degradation of 100 nm AlGaN/GaN HEMTs under DC and 10 GHz stress conditions has been compared and a promising median lifetime of more than 2000 h under RF stress in air at a drain voltage of 15 V and an average channel temperature of 230°C has been achieved. It has been found that the devices degrade faster under RF stress compared to DC stress. Physical failure analysis using electroluminescence imaging, TEM and EDX cross-sections parallel and perpendicular to the gate finger shows that the local oxidation induced pit formation beside the gate foot and the interdiffusion of Pt with Al, Ga and N are the main failure mechanisms causing the degradation in saturation current and increase of leakage current of DC stressed devices.

In this work, the deep-level trapping behaviour of GaN-on-GaN current aperture vertical electron transistors (CAVETs) is characterised by means of current transient measurements and compared to AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on the same wafer. To the best of our knowledge, this represents the first analysis of deep-level traps in a GaN-based CAVET. In both structures, a single deep-level with an activation energy of (1.086 ± 0.015) eV (CAVET) and (0.812 ± 0.032) eV (HEMT) is found to dominate the observed transient responses.

This work presents a Si-substrate removal technique for AlGaN/GaN devices on PCB carriers. The Si-removal method is explained and experimentally applied to PCB-embedded AlGaN/GaN-on-Si devices. The PCB-embedding package is reopened at the thermal pad by laser-removal and the Si-substrate is removed by wet chemical etching. The paper presents a direct comparison of the electrical characteristics for devices before and after Si-removal. Different substrate related effects are observed and investigated. The pulsed drain currents degrade after Si-removal, due to the absence of the thermal substrate capacitance. Furthermore, the dynamic on-state resistance is increased by surface trapping on the exposed backside. Measurement results are discussed and physically interpreted. The on-state resistance is unaffected in the range of $175 \mathrm{m}\Omega$ before and after Si-removal. The measurements show an increase of the off-state voltage from 600 V to 1400 V for devices after Si-removal.

A systematic investigation of the effect of temperature and electric field on the degradation of 100 nm AlGaN/GaN HEMTs stressed under on- and off-state conditions has been carried out. The shape of the degradation behavior is analyzed and compared between stress conditions. The shape parameter of an Avrami-model was found to be reduced at higher temperatures. Failure analysis was performed by delayering with subsequent SEM and AFM investigation of the semiconductor surface. All devices showed surface damage in the vicinity of the drain-sided gate-edge. Devices stressed at high voltage and high temperature exhibited more and deeper pits than devices stressed at low drain-bias and low temperature, even though all devices have been stressed to the same electrical degradation of 10 % decrease in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSS</sub> .

This paper gives the state-of-the-art (SOA) of the technological development and the reliability status of deep-submicron Gallium Nitride (GaN) high-electron mobility transistors (HEMTs) with gate lengths of 100 nm or below. Several process technologies are discussed and epitaxial, process options, and reliability are compared. Promising GaN MMIC device results are also provided leading to improved GaN G-band operation at frequencies near 200 GHz.

In this paper we report on the development of a 0.50 μm AlGaN/GaN on SiC technology optimized for 100-V operation. Load pull measurements reveal a power density of more than 17 W/mm and a power-added efficiency of 77.3 % at a frequency of 1.0 GHz and a drain supply voltage of 100 V. Experimental data at 125 V even shows a power density in excess of 20 W/mm. To the authors' knowledge, the demonstrated PAE of 77.3 % is the highest ever reported in L-band for 100-V operation.

This work investigates a new approach of a multistage cascode. The concept is applied as intrinsic structure in an AlGaN/GaN-on-Si technology. The fabricated device achieves an off-state voltage >600 V and an on-state resistance of 14 Ω mm. A special pull-down pin is connected to the source of the highest segments. This pin can be used for characterization and is intended to drive further stacked cascade segments. Thus, integrated multi-stage cascodes are found suitable as flexible device for high voltage applications.

We investigated the voltage- and temperature -dependent degradation of AIN/GaN high electron mobility transistors with gate lengths of 70 nm and 100 nm. The devices under test were dc stressed in semi-on-state conditions at constant power dissipation of $4.5\displaystyle \frac {\mathrm {w}}{\mathrm {m}\mathrm {n}}$ for approximately 200h or until the drain saturation current $I_{\mathrm {D}\mathrm {S}\mathrm {S}}$ dropped by 10 %. To examine whether a Arrhenius like temperature acceleration and additionally voltage acceleration can be ascertained, the channel temperature and stress voltage were varied. In our tests, both acceleration factors could be confirmed and are shown to be interdependent. Arrhenius fits resulted in activation energies between 0.80 eV and 1.12 eV. A generalized Eyring approach is used to model the combined acceleration by temperature and voltage as well as their interdependency.

The effect of gate technology and semiconductor passivation on the switching speed and device reliability has been investigated. By reducing the parasitic capacitances and reducing the passivation induced surface charge density a median lifetime of around 10(6) h at a channel temperature of 125 degrees C and a current-gain cut-off frequency of 74 GHz for a T-gate technology has been achieved. By electroluminescence and TEM cross-sectioning of a stressed device a local inhomogeneous pit formation process was found as the major degradation mechanism for the decrease of the saturation current.

The epitaxial structures are grown by metal-organic chemical vapor deposition on 4-inch Si(lll) substrates. First, a graded AlGaN buffer is deposited to mitigate lattice and thermal coefficient mismatches. Second, a thick GaN layer with an AIN interlayer is grown, followed by the AIGaN/GaN heterojunction. The structure is capped by a p-doped GaN layer. Mg is used as acceptor with a concentration around 3-4×10 19 cm -3 according to secondary ion mass spectrometry. The structural properties of the samples are investigated using high-resolution X-ray diffraction, see Figure 1. The thickness (approx. 15 nm) and composition (around 20% Aluminum) of the AlGaN barrier are well within the parameter space to obtain normally-off devices [1]. The p-doped GaN cap has a thickness around 53 nm. A two-step dry-etch process based on a Cl 2 /N 2 /O 2 plasma [2] has been adapted in order to remove the p-doped GaN cap, see Figure 2. The process is characterized by a large process window in order to provide high reproducibility.