In this study, we investigate low frequency noise under the reverse body bias conditions from sub-threshold to moderate inversion regime, in order to experimentally extract the impact of depletion capacitance with the reverse body bias. From 1/ ${f}$ noise measurement for small-area conventional ${n}$ MOSFETs, the reverse body bias is not influenced on the coulomb scattering process, even though the depletion capacitance was influenced by body bias. Furthermore, small gate-to-bulk coupling with smaller depletion capacitance caused by reverse body bias reduced Random Telegraph Noise as well as flat-band fluctuations of gate voltage noise spectral density. These results suggest that reverse body bias is applicable to the low power and high signal-to-noise ratio for low current operation.

This paper reviews the development of compact modeling technology of MOSFETs for RF (Radio Frequency) and millimeter wave applications. Thanks to the recent renovation of measurement techniques it is possible to generate big data on the basis of automated S-parameter measurement. Accordingly, MOSFETs' compact models are already capable of providing accurate statistical simulation by the use of big data. In this paper, unique approach to revise existing MOSFETs' compact models is demonstrated. Our study has shown proposed model can give accurate statistical distribution of high frequency behavior of MOSFETs via single device level and circuit level.

The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

In this study, we investigate low frequency noise under the reverse body bias conditions from subthreshold to moderate inversion regime with 1/f noise measurement for small-area conventional nMOSFETs. The reverse body bias is not influenced on coulomb scattering process, even though the depletion capacitance was influenced by body bias. Furthermore, gate-to-bulk coupling was reduced flat-band fluctuations. These results suggest that reverse body bias is applicable to the low power and high signal-to-noise ratio for low current operation.

This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

This paper reviews the development of compact modeling technology of RF (Radio Frequency) MOSFETs. Author, who was involved in the research and development of RF compact models for many products, will look back the footprints of the important technical issues, which are still essential for the next generation of IoT and wireless applications, and gives outlook of the future related technology developments.

The report focuses on an optimization scheme of advanced MOSFETs for designing power efficient circuits. For the purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift compared to the long-channel MOSFET, provides the consistent measure as the short-channel effect on device performance degradation. However, the circuitry performances degradation such as the power loss cannot be predicted sufficiently by the short channel effect alone. It is demonstrated that the power efficient circuit design can be achieved by minimizing the additional leakage current caused by the short-channel contribution.

A striped inductor and its utilization of a voltage-controlled oscillator (VCO) are studied with the aim of suppressing phase noise degradation in K-and Ka-bands. The proposed striped inductor exhibits reduced series resistance in the high frequency region by increasing the cross-sectional peripheral length, as with the Litz wire, and the VCO of the striped inductor simultaneously exhibits a lower phase noise than that of the conventional inductor. Striped and conventional inductors and VCOs are designed and fabricated, and their use of K-and Ka-bands is measured. Results show that the Q factor and corner frequency of the striped inductor are approximately 1.3 and 1.6 times higher, respectively, than that of the conventional inductor. Moreover, the 1-MHz-offset phase noise of the striped inductor's VCO in the K-and Ka-bands was approximately 3.5 dB lower than that of the conventional inductor. In this study, a 65-nm standard CMOS process was used.

Current-reuse concurrent 800 MHz / 1.9 GHz dual-band amplifier has been studied. Proposed amplifier consists of PMOS cascode amplifier and NMOS cascode amplifier with current-reuse topology and individual inductive source degeneration matching circuits to obtain sufficient input matching for both 800 MHz / 1.9 GHz. Measured |s11|, |s21|, and |s22| exhibit approximately −7 dB, 9 dB, and −5 dB at 800 MHz and −18 dB, 7 dB, and −11 dB at 1.9 GHz, respectively. IP1dB at 800 MHz is −24.6 dBm and that at 1.9 GHz was −13.6 dBm, also, IP2 showed approximately −32 dBc and IP3 at 3 GHz is approximately −48 dBc. Chip is fabricated using 65 nm standard CMOS process with UTM and total power consumption is 10.8 mW.

Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

Flicker noise suppression of K-Band scaled-CMOS VCO using striped inductors have been studied. The phase noise degradation is a problem of high-frequency VCO. Especially phase noise which arise from flicker noise is the most significantly in the case of using noisy scaled CMOS process. In this work, we present flicker noise contribution phase noise improvement using striped inductors. Striped inductors have been studied for thermal noise contribution phase noise improvement due to skin effect suppression, however, they are also effective to suppress flicker noise contribution phase noise improvement since 2nd harmonic reduction by its higher parasitic capacitance. The experimental results show VCO's corner frequencies between thermal noise contribution region and flicker noise contribution region were 25 and 55% reduction using striped inductor with 2 and 4 μm metal space, respectively. A 1-MHz-offset phase noise show -104, and -103 dBc/Hz using 2 and 4 μm metal space striped inductor, respectively. It exhibits approximately 5 dB better phase noise than conventional inductor VCO. The process technology using all experiments were 65-nm standard CMOS with thick Cu metal.

Millimeter wave striped inductor VCO has been studied. To obtain lower phase noise, the enhancement of Q-factor of inductor is essential, although it is difficult in the case of dozens gigahertz region due to skin effect. In our previous results, quasi-millimeter wave striped inductor VCO can be obtained lower phase noise by suppression of skin effect. In this work, we have been investigated corner frequency of striped inductors and the phase noise of several oscillation frequencies VCO with striped inductor. The corner frequency of striped inductor achieves approximately two times higher than that of conventional inductor. The minimum phase noise of several types of striped inductor VCOs show −106, −102, and −97 dBc/Hz at 1-MHz offset from fosc = 23, 25, and 40 GHz, respectively. It exhibits 2–4 dB better phase noise compare than conventional inductor VCO. The process technology using all experiments is 65-nm standard CMOS with thick Cu metal.

This paper presents the strategy of MOS varactor's high-Q optimization, a novel scalable model for the quasi-millimeter-wave MOS varactors, and confirmation results by discrete MOS varactors and VCO measurements. To realize a high-Q MOS varactor in the quasi-millimeter-wave region, low MOS varactor capacitance and low series resistance of unit cell are essential. Downsizing is a key to realize both low capacitance and low resistance. However, it is induced by C-max/C-min reduction, simultaneously. Therefore, scalable MOS varactor model is necessary to use. optimum MOS varactor to cover various application requirements using same process. Decreasing the MOS varactor's size of W/L = 2 mu m/2 mu m to 0.5 mu m/0.26 mu m, the Q factor increased sevenfold at f = 20 GHz but C-max/C-min is reduced by 60%, by using conventional PSP model, an error of approximately 20% is shown. Proposed model has been improved its accuracy from 18.9% to 0.2% for N+ MOS varactor and from 22.1% to 0.8% for P+ MOS varactor, for minimum size of MOS varactor even if model covers wide dimension range. Also, it has been confirmed this model is covered in two types of layouts. Oscillation frequency and phase noise also have been confirmed by three types of 22 GHz VCOs. The accuracy of oscillation frequency is less than 2.5% and that of phase noise at 1 MHz offset from carrier is less than 5 dB.

Striped inductor has been implemented to quasi-mm-wave voltage-controlled oscillator (VCO) to improve Q-factor. Since skin effect is significantly degrades Q-factor of inductor in this frequency region, the phase noise of VCO is degraded. Proposed striped inductor can be improved its Q-factor, hence, the phase noise of VCO is improved. The phase noise of designed and fabricated VCO shows -106 dBc/Hz at 1MHz offset from 21-GHz oscillation frequency. It exhibits 5 dB better phase noise compare than conventional inductor's VCO. The process technology of designed and fabricated VCO is 65-nm standard CMOS with thick Cu metal.

High-Q and scalable MOS varactor for mm-wave VCO has been studied. To realize high-Q varactor in mm-wave region, low varactor capacitance and low series resistance of unit cell are essential. Since low varactor capacitance and low series resistance are impossible to realize simultaneously, optimization and scalable model are necessary. This paper presents strategy of high-Q optimization, a novel scalable model for mm-wave varactor, and confirmation results by VCO measurements. The Q of small-geometry varactor improved 30 times at f = 30 GHz. The novel scalable varactor model improved its accuracy from 21.9% to 1.7%.