The selective emitter (SE) design, featuring lower doped areas between the front contact fingers and higher doped areas underneath the front metallization, is crucial to improve the performance at the front side of a monocrystalline (c-Si) silicon solar cell. One of the most interesting and promising low-cost SE process consists of the screen printing of a phosphorus-doped paste, allowing a separate optimization of the doping profiles in the metallized and nonmetallized front-side areas. By referring to this kind of process, this paper presents a simulation study with a decoupled analysis on the effect of the lowly doped and highly doped profiles on the performance of an SE solar cell, by means of 2-D electro-optical numerical device simulations. Moreover, by exploiting the 2-D modeling, the effect of the alignment tolerance used in the SE diffusion process for the subsequent metallization process has been also investigated. Numerical results show that the adoption of an optimized design for the SE cell can lead to an efficiency improvement above 0.4%abs compared with the 75 Ω/sq homogeneous emitter reference cell.

High efficiency silicon monocrystalline solar cells commonly adopt point contacted rear surfaces to reduce the recombination losses in the rear side of the device. However, the reduction of the rear contact surface leads to an increase of series resistance losses. Modeling and analysis of rear point contact solar cells is strategic to optimize the device design by taking into account several competing physical mechanisms. Owing to their complicated geometries, the analysis of these devices requires three-dimensional (3-D) numerical simulation. In this work we analyze the influence of the most important geometrical and electrical parameters on the conversion efficiency of rear point contact solar cells.

Employing Ga 2 O 3 (Gd 2 O 3 ) as gate dielectric and Si-doped GaAs as conducting channel, depletion-mode GaAs MOSFETs were fabricated. DC I – V and transfer curves show no pinch-off and drain current hysteresis. Etching a thin layer from the top of Ga 2 O 3 (Gd 2 O 3 ) in the gate region before gate metal deposition leads to full pinch-off and significantly reduces the drain current hysteresis. This process may remove the contaminated Ga 2 O 3 (Gd 2 O 3 ) due to exposure to chemicals and prior processes, and thus results in a clean gate metal to oxide interface. The clean gate metal to Ga 2 O 3 (Gd 2 O 3 ) interface also leads to higher DC transconductance, higher unity current gain cut-off frequency as well as higher unity power gain cut-off frequency as compared with GaAs MOSFET devices with a contaminated metal/oxide interface at the gate.

The observed initial gain degradation of AlGaAs/GaAs heterojunction bipolar transistors under current stress was investigated. The change in device characteristics is attributed to a dissociation of passivating hydrogen in the base layer during stress. The hydrogen passivation occurs during the implant isolation process. An activation energy of 0.75 eV was measured for the junction temperature dependence of the dissociation process.

Employing Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as gate dielectric on GaAs, prepared in a multi-chamber MBE system, has resulted in a low interfacial density of states (D/sub it/). The gate oxide is subjected to photoresists, solvents, water, and air before metallization, and as a consequence, contamination of the gate oxide is inevitable. The authors have studied the effects of gate oxide cleaning and etching before metallization on the DC and RF characteristics of depletion-mode GaAs MOSFETs with Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as gate dielectric.

DC characteristics of a depletion-mode (D-mode) GaAs MOSFET with a thin Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) gate dielectric layer (74 /spl Aring/) show low gate leakage current, negligible drain current hysteresis and higher than 10 V gale-drain two-terminal breakdown voltage. Compared to MESFET with the same gate length, channel material and fabricated by the same process, the GaAs MOSFET shows higher unity current gain cutoff frequency (Ft). The higher Ft for the MOSFET than that of the MESFET agrees with earlier theoretical predictions.

As process technology advances, we will see SoC systems with millions of digital gates combined with RF circuits operating in the tens of GHz.

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.

We report experimental results demonstrating the use of transient enhanced diffusion (TED) caused by silicon implant for "tuning" boron out-diffusion. The effect was measured as a function of the silicon implant dose and anneal temperature, and a range of boron junction depth movement from almost none up to 81 nm was observed with increasing TED at 750 degrees C. The diffused profiles could be approximated by using a modified solubility limit model to describe the enhanced boron diffusion and clustering. However, by using a more sophisticated continuum model based on atomistic calculations, excellent agreement with the measured profiles could be obtained. In addition, the fit to the measured data yields the fraction of boron present in BI2 precursor clusters after silicon implant as a function of the silicon implant dose. Two possible applications of the TED "tuning" are discussed, with device simulations which show that the effect is sufficiently large to tune the base width of a bipolar device from being depleted to that suitable for a high performance device.

Inductors fabricated using CMOS technologies based on epi/p/sup +/ substrates are severely degraded because of eddy current losses in the substrate. We propose and demonstrate a modified substrate structure, which addresses the conflicting goals of high inductor quality-factor and high latch-up immunity. Results include fabricated inductors with Q-factor as high as 16.

We report a new super self-aligned graded SiGe base transistor that uses high energy implantation, rather than epitaxial growth, to form the sub-collector region. This new inexpensive process yields a device with f/sub T/ of 52 GHz and f/sub max/ of 70 GHz with the addition of only 4 lithography levels over our 0.25 /spl mu/m CMOS technology without any changes to the existing process steps. Also, we demonstrate 4:1 multiplexer and 1:4 demultiplexer circuits using this technology that show excellent performance at 10 Gbit/s.

An alternate criterion of failure for very thin oxides is proposed that can reliably detect the occurrence of both soft breakdown and hard breakdown during accelerated stress tests. We show that an increase in current noise that occurs at oxide breakdown can be detected rapidly with commercial test equipment, even when no discernable voltage drop can be observed. As an initial test vehicle for implementation of a noise test, we chose the JEDEC standard J-ramp test. This test can be implemented with very minor software changes and can detect both hard and soft breakdowns for 2-6 nm oxides.

Inductors are essential for fully integrated, complex RF circuits such as single chip radios. Both high Q, Q > 15, and high precision, +/- 2 percent, inductors are needed to meet phase noise specifications for on-chip VCO's and for reactive impedance matching to improve power transfer and linearity. We describe the design, test and simulation of self-assembled, micromachined inductors lifted away from the substrate by tensile stress in the metallization. The air gap reduces the capacitive coupling to the substrate, increasing both the Q and self-resonant frequency. For 2nH inductors we have measured Q-14 at 2GHz, with process variation < 2 percent. Increased temperature and current strongly increase the loss, but do not effect the inductance. The inductors are also relatively insensitive to mechanical excitation, with forces approximately 30g's required to significantly modulate the inductor loss under resonant excitation. Extensive EM simulations of this design methodology suggest that we should be able to reach Q > 25 at 2GHz and maintain 10GHz. We also compare these results with state of the art fully integrated Si RFIC planar inductors.

At present there are two common types of integrated circuit inductor simulation tools. The first type is based on the Greenhouse methods, and obtains a solution in a fraction of a second; however, because it does not use solutions of the inductor charge and current distributions, it has limited accuracy. The second type, method of moments (MoM) solvers, determines the charge and current variations by decomposing the inductor into thousands of sub elements and solving a matrix. However, this process takes between minutes and hours to obtain a reasonably accurate solution. In this paper, we present a series of algorithms for solving inductors, of radius small compared to the wave length of the electrical signal, that equal or exceed the accuracy of MoM solvers, but obtain those solutions in roughly 1 second.

The Johnson limit predicts that due to fundamental material limitations, the f/sub t/BV/sub ceo/ product for Si bipolar transistors cannot exceed 200 GHz-V. Since this limit ignores many practical components, it should not be achievable experimentally. In light of the fact that results reaching this limit have been reported, we have reevaluated such fundamental limits, and have found that this number should be much higher.

Porous Si layers up to 250 /spl mu/m in thickness are used to isolate spiral inductors from low resistivity substrates. Wafer curvature and SIMS analysis are done to address the manufacturability issue of porous Si. Spiral inductors with a single level Al on 2-inch, p-type substrates of 0.008 /spl Omega/-cm resistivity are demonstrated with Q=5.0 at 1.8 GHz for an L of 9 nH. Large inductors with L/spl sim/150 nH have been shown with the first resonance frequency at 1 GHz. The expected performance potential as well as factors that could be limiting the Q are discussed.

A 0.25-/spl mu/m modular high-energy implanted complementary BiCMOS (HEICBiC) technology has been developed for wireless-communication VLSIs. The technology demonstrates a high f/sub T/=52 GHz and a high f/sub T/BV/sub CEO/=160 GHz-V for single-poly emitter NPN transistors and a high f/sub T/=10.7 GHz for implanted-emitter PNP transistors. It is one of the best results for single-poly BiCMOS/bipolar technologies without an epitaxial buried collector. In comparison with 0.25-/spl mu/m NMOS, HEICBiC shows lower power consumption and higher RF performance.