Today’s design of computer systems is mainly limited by the achievable I/O bandwidth. Chip designers try to avoid this barrier by designing larger and larger chips. Package designers on the other hand are facing ICs with smaller and smaller pad pitches for more and more I/Os. This traditional separation between chip and package design blocks new solutions. But a close co-operation of chip and package designers allows new partitioning options by combining area I/O with new chip design. The co-operation brings up more and faster I/Os which are easy to connect. The achievable improvements are exemplified on a generic microprocessor system design. 1 Motivation State of the art processors show ever increasing internal clock rates to improve performance. But the external clock rate as well the I/O bus width hardly match this trend as shown in the roadmap (table 1). It was tried to overcome this discrepancy of off-chip bandwidth to on-chip speed by adding several levels of caches, which enlarges the maximum latency more and more [3]. The larger I/O buses proposed in the roadmap are difficult to connect to the outside. Furthermore, the package parasitics slow the speed down. Therefore, the IC designers as well as the package designers have to co-operate to provide new solutions based on area I/O as proposed in section 2. To illustrate the achievable improvements, they are discussed on a microprocessor system design in section 3. 1998 2001 2004 2007 2010 Year 200

Both cost and quality are important features when manufacturing today's high-performance electronics. Unfortunately, the two design goals (low) cost and (high) quality are somewhat mutually exclusive. High testing effort (and thus, quality) comes with a considerable cost, and lowering test activities has significant impact on the delivered quality. In this paper, we present a new structured search method to obtain the best combination of these two goals. It features a Petri-net oriented cost/quality modeling approach and uses a Pareto chart to visualize the results. The search for the Pareto-optimal points is done by means of a genetic algorithm. With our method, we optimize a manufacturing process for a global positioning system (GPS) front end. The optimized process clearly outperformed the standard fabrication process.

This article presents the RF characterization results of a large-area MCM-D technology developed within the EU LAP project. Microstrip lines were simulated, designed, and manufactured in several material combinations. Measurements up to 120 GHz showed good coincidence between simulation and reality. Future work is dedicated to filters and antennas in the 77 GHz range.

This paper presents the results of investigations on integrated inductors for a new low cost MCM-D substrate technology. The results are focused on the analysis of design options and design parameter for planar spiral inductors. Measurements on test structures were used to quantify process tolerances and inductor performance and to set up accurate models for EM-simulations. Simulation results of many different inductor configurations and layouts were compared in terms of inductance L, quality factor Q and area A. The goal was to give a better understanding of inductor behavior to geometry changes and to offer inductor design guidelines for RF system designers. Special attention was given to inductor cost, driven by area consumption.

Very early in an electronic design cycle the physical buildup of a system, such as bonding method, substrate technology, and number of layers, needs to be chosen before any layout is performed. But when developing high density systems, a huge number of technology choices are available, each having impact on various aspects of the system performance. This paper describes virtual prototyping as a method for systematically analyzing and choosing the suitable buildups and selecting one of them in a cost-performance analysis for implementation and layout. Unlike former design advisors, our method analyzes several possibilities in parallel, allowing for a better design space exploration. The framework is implemented in the Java based tool JavaCAD, JavaCAD manages the different buildups and provides a size/layer count estimation for all first level interconnect/packages on various substrate technologies. It calculates the component footprints, analyzes the routing with as few data as available and allows cost estimation of all feasible buildups. The benefits of our approach are illustrated in the design of a 9:4 satellite switch operating at 2.4 GHz.

Abstract Large Area Processing for thin film substrates can be used to reduce the cost per layer per area significantly. Various process setupsexist to achieve this goal, and they vary in terms of process tolerances and cost. As different process tolerances result in differentperformance tolerance bands of the produced structures, customers may want to choose the right process to obtain sufficient quality.This paper presents the cross links between the two aspects performance and cost. Taking two process setups with diverse interconnectmetallization width and dielectric thickness uniformity tolerances, the authors demonstrate the impact on integrated RF elements asmicrostrips, inductors, and antennas.Our findings show that it is suitable to offer customers two alternative types of processes: a tighter-tolerance process for high-performance RF applications, and a lower-cost process for less demanding products. Key words: Process Tolerances, RF, Integrated Antennas, and Activity CostModeling

In this paper, we present a pre-layout yield estimation approach to assess the impact of changing design rules to overall substrate cost. Introducing a density factor for interconnect substrates together with a simplified yield model, thus accelerating the "short failure" critical area estimation, a preliminary design rule trade-off is feasible.In order to assess a possible cost impact when changing the design rules, we used a nine-chip Pentium multi-chip module as a case study, where we re-calculated substrate sizes and first pass yields using our model. The results showed that there is only a narrow window of opportunity to profit economically from altering the rules. (C) 2001 Elsevier Science Ltd. All rights reserved.

In this paper we present a yield model detailing the impact of changing design rules to overall substrate cost. Using a simple yield model, we extracted the critical area for the “short/open failure” model mainly present for pure interconnect substrates. Introducing a density factor, the “short failure” critical area extraction could be simplified massively. To quantify the cost aspects of changing the design rules, we used the case study of a 9-chip Pentium MCM, re-calculating substrate sizes and first pass yield using our model. The results showed that there is only a very narrow window of opportunity to gain economically from increasing the design rules.

The Large Area Processing for thinfilm substrates can be used to reduce the cost per layer per area significantly. Various process setups exist to achieve this goal, and they differ in terms of process tolerances and cost. As different process tolerances result in different performance tolerance bands of the produced structures, customers may want to chose the right process to obtain sufficient quality. This paper presents the cross links between the two aspects quality and cost. Taking two process setups with different interconnect metalization width and dielectric thickness uniformity tolerances we demonstrate the impact on integrated RF elements as microstrips. inductors, and antennas.Our findings show that it is suitable to offer customers two alternative types of processes: a tighter-tolerance process for high-performance RF applications, and a lower-cost process for less demanding products.

Two dedicated RF test vehicles (RF-TV) have been designed to characterise the high frequency performance of a new low-cost thin film (MCM-D) technology, fabricated on large area panels (LAP). Previous investigations revealed the capabilities of the new LAP technology to be used at frequencies up to 110 GHz. Test structures for transmission measurements, lumped components such as spiral inductors or plate capacitors and distributed components such as bandpass filters and couplers are included on the RF-TV1 and RF-TV2. This paper presents the design and the simulation results of integrated Lange couplers at 20 GHz and patch antennas at 77 GHz.

In this paper we present the MCM implementation of a 9:4 satellite switch in MCM-C/technology operating at frequencies up to 2.4GHz. The MCM contains two ASIC switches, four DiSEqC controllers and an inverter. RF interconnections are realized as coplanar lines in order to obtain sufficient shielding and impedance control. With this implementation, ii was possible to connect the ASIC outputs without a matching network due to the short distances. Also the DiSEqC controllers, formerly not included, could be moved into the module achieving a more complete partition and enhancing functionality towards digital switching. Measurements,revealed that the fabricated module is fulfilling its specs, although a redesign is justified to fully exploit the technology's performance. With this switch MCM it is possible to double the functionality of a switch daughter card on the same form factor.

Passive components integrated into a high-density substrate can be a tolerable way to overcome the size and manufacturing limits of SMD passives mounted onto the system board. Still, this technology is perceived as being "too risky" and not cost effective. In this paper we propose a "passives optimized" solution combining the advantages from both SMD and integrated technology and avoiding the respective drawbacks. Exemplified by a GPS receiver front end, we present a methodology to assess the possible benefits when using the mixed technology.

Both cost and quality are important features when manufacturing high performance electronics. Unfortunately, the two design goals, (low) cost and (high) quality, are usually somewhat mutually exclusive. High testing effort (and thus quality) comes with a considerable cost, and sparing the test has significant impact on the delivered quality. In this paper, we present a new structured search method to obtain the best combination of these two goals. It features a graphical oriented cost/quality modeling approach and uses a Pareto chart to visualize the results. The search for the Pareto-optimal points is done by means of a genetic algorithm. With our method, we optimize a manufacturing process for a global positioning system (GPS) front end, clearly outperforming a standard fabrication set-up.

This paper presents new process monitoring strategies for low cost high density substrates manufactured on large area panels. By increasing the panel size from today 's 4 x 4 inch(2) rep to 24 x 24 inch(2) the EU LAP project is reaching the costs target of US$1/inch(2)for MCM-D substrates. But therefore it is essential to keep the substrate yield on large panels as high as on small panels. With this goal in mind we face complete new monitoring challenges and cost-yield trade-offs. The presented monitoring strategies are laid out to minimise the area consumption, maximise the failure coverage and avoid additional process steps. A case study at the end of the paper shows the benefits in terms of field and cost when using the new strategies.

The ultra-miniature GPS receiver by mu-blox in high-density laminate technology currently uses wire bond interconnect for its digital part. This paper explores the cost saving potential when switching to chip-scale packages (CSP) before starting an expensive redesign. The evaluation includes a detailed footprint analysis together with a cost/yield calculation. The footprint analysis shows that by using CSPs with ball pitches down to 0.65 mm it is possible to loosen the substrate design rules. This potential cost reduction, together with improved manufacturing yield, compensates for the investment of the CSP packaging and substrate redesign, still leading to lower overall cost. Thus, CSP packaging could be a feasible solution for the next GPSMS1 redesign.

To date designers seek to achieve ever smaller systems with ever more functionality, but more and more they face the interconnection technology as a show stopper. To overcome this bottleneck we propose a chip-package codesign approach; a close cooperation between chip and package designers exploiting the synergism. Our approach distributes the on-chip pads all over the IC area near the pads associated core area. This technique results into smaller ICs with more and faster I/Os being much easier to package. In this paper, a case study for a Pentium class system shows why other approaches such as wire bond, re-routing and chip size package (CSP) have shortcomings. Finally, we present an outlook to new system architectures that are enabled by area I/O: A processor system with first level cache on separate ICs instead of being integrated on the CPU itself.

This paper describes an integrated development tool for analog fuzzy controllers which exploits analog hardware implementation and fuzzy logic flexibility to allow an easy and extremely low-cost synthesis of non-linear control laws. The core of the final implementation is a modular general-purpose analog fuzzy engine (AFE) with good speed performance and built-in temperature compensation. To ease field prototyping, a digitally-programmable version of AFE is provided with a software layer computing the biasing voltages needed by the circuit to fit numerical data and/or linguistic rules specified by the users. Once that the application is fine-tuned, a further software module is able to generate an optimized version of AFE dedicated to the task. An example application shows that this approach can lead to the implementation of effective analog controllers fulfilling industrial requirements.

Today's high-density packaging technologies make early attention to most factors essential in the design of successful products. A process-oriented, scalable cost-modeling tool, the Modular Optimization Environment (MOE), enables a continuous cost-quality-performance trade-off analysis throughout the design and manufacturing process.