This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work seamlessly with existing sequential linear decompressors. Experimental results obtained for industrial designs demonstrate the effectiveness of the proposed method at reducing TDV in high compression configurations.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.

Solar array rotation mechanism provides a hinged joint between the solar panel and satellite body, smooth rotation of the solar array into deployed position and its fixation in this position. After unlocking of solar panel (while in orbit), rotation bracket turns towards ready-to-work position under the action of driving spring. During deployment, once reached the required operating angle (defined by power subsystem engineer), the rotation bracket collides with the fixed bracket that is mounted on body of the satellite, to stop rotation. Due to the effect of collision force that may alter the rotation mechanism function, design of centrifugal brake is essential. At stoppage moment micro-switches activate final position sensor and a stopper locks the rotation bracket. Design of spring and centrifugal brake components, static finite element stress analysis of primary structure body of rotation mechanism at stoppage moment have been obtained. Last, reliability analysis of rotation mechanism is evaluated. The benefit of this study is to aid in the design of rotation mechanism that can be used in micro-satellite applications.

This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture.

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

Purpose: Fusion of subtalar arthrodesis is achieved in 94% of cases. There is a significant superficial cutaneous and neurological risk. Since 1985, we have performed partial arthrodesis using curettage-filling of the tarsal sinus via a minimally invasive approach. We wanted to know whether this technique decreases morbidity while preserving maximal rate of fusion. Material and methods: We reviewed 52 patients (55 arthrodeses) operated on by the same surgeon. Immediate weight-bearing was allowed in all patients with a walking boot cast worn for ten weeks. We studied speed of fusion, the hindfoot axis, the development of complications, and the functional outcome (Kitaoka score). Results: Fusion was not achieved in one case at ten weeks. Cutaneous necrosis occurred on one patient who had required a wide approach for other procedures. There was one superficial infection and one reflex dystrophy. Defective residual alignment was observed in six feet where the deformation could not be reduced preoperatively. The mean function score was 39/100 preoperatively and 86/94 postoperatively. Conclusion: This technique provides excellent results with minimal morbidity but can only be proposed if the misalignment can be reduced preoperatively.

Purpose of the study We reviewed retrospectively 24 feet with sequelae of transtalar process fractures of the calcaneum in order to identify the lesion pattern and determine optimal management options, both for acute and sequelar lesions.Material and methods There were fourteen men and nine women, mean age 42 years (19-73). Twenty-three had subtalar osteoarthritis, eight had calcaneocuboid osteoarthritis, and fifteen had lateral submalleolar conflicts. There were twelve fibular tendon dislocations or fissurations, three tarsal tunnel syndromes, and two plantar splinters. Prior to treatment, all patients complained of pain. Preoperatively, walking distance was less than 500 m for thirteen patients, 2000-3000 m for four, and greater than 3000 m for five. Mean subtalar joint motion was 30% (0-100%) compared with the healthy side and mean frontal misalignment of the rear foot was 6° vaigus. Physical examination, podoscopy and x-rays were obtained in all patients. The Kitaoka score was noted.Result Mean follow-up was 36 months (24-72). Sequelae were treated with a single procedure or with combinations: subtalar arthrodesis (n = 23) including one in association with calcaneocuboid arthrodesis, tension on fibular tendons (n = 7), neurolysis of the posterior tibial nerve (n = 3), resection of plantar splinters (n = 2), resection of the lateral shell (n = 14), and osteotomy (n = 2) to lower the greater tubercle of the calcaneum because of pain when wearing shoes. The mean Kitaoka function score was 31.7/100 (14-79) preoperatively. After treatment, the mean score was 81.7/100 (31-94), giving a 73.2% gain. The outcome was considered good in sixteen feet, fair in six, and poor in two. Mean walking distance was greater than 3000 m for 18 patients. Mean frontal misalignment of the rear foot under loading was 4.5° valgus and the podoscopy demonstrated flat foot in thirteen patients. Three subtalar arthrodesis required revision for nonhealing.Discussion Initial treatment of a fracture, particularly an articular fracture, of the calcaneum must avoid disabling postoperative pain and shoe wearing problems. These sequelae basically concern: subtalar and calcaneocuboid arthritis, lateral submalleolar conflict, fibular tendon injury, plantar splinters, tarsal tunnel syndrome, loss of height, and misalignment of the rear foot. At the sequelar stage, the physical examination is primordial to confirm the lesion and search for any complication which could develop later postoperatively when walking distance becomes longer. For nine patients with residual pain, four resulted from lesions which were missed at the preoperative physical examination. Arthrodesis of the subtalar joint should be preferred over realignment of the rear foot and can be associated with the treatment of conflicts. This management scheme allows treating during a single operative time all sequelae, thus limiting recovery time. A scan of the ankle and foot with or without opacification of the fibular tendons is needed to confirm the physical examination which, for us, remains the key to successful surgery.

Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually induce both faults and the TDF test set can contain unnecessary test patterns for proper screening of this type of defect. The inline resistance fault (IRF) model more accurately represents this defect type and is studied in depth in This work. ATPG experimental results show that IRF patterns can be generated 1.4 to 1.8 times faster with 45% to 58% fewer patterns than traditional TDF patterns. IRF and TDF pattern test results are presented and show that the more expensive TDF remains a more comprehensive test than IRF as expected, but that the quality impact of using only the IRF test set is minimal, especially when combined with effective IDDQ outlier screening such as statistical post processing. Additionally, a methodology is presented for the determination of the number of delay defects that behave according to each model from the test data alone, which is necessary to accurately determine delay defect coverage from multiple test coverage metrics.

Eleven patients (10 men and 1 woman) with a mean age of 32 years (range: 16-61 years) and a mean follow-up of 12 years (range: 2-21 years) were studied retrospectively after ipsilateral fibular transposition. The cause of tibial nonunion was a motor vehicle collision (MVC) in eight patients, a fall from a window in one, an adamantinoma in one, and osteomyelitis in one. There was one type I and eight type IIIb open fractures according to the Gustilo classification, and the nonunion was infected in seven patients. Healing of the tibial defect was obtained in eight patients, after a mean interval of 10.5 months. In the patient with the adamantinoma, resection of the tumour left a 22 cm defect in the tibia. Two patients required amputation for acute local infection. Seven of the eight patients in whom tibial union was achieved were able to walk with no aids. The authors conclude that transposition of the ipsilateral fibula is a valuable component of the therapeutic armamentarium and a salvage procedure for patients with multi-operated, infected or uninfected, tibial nonunion.

This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-on-Chip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive, wireless, and data communication applications are provided. These results demonstrate that EDT, with no performance impact, little area overhead, and minimal impact to the flow, results in a significant reduction of scan test data volume and scan test time while maintaining the test quality levels.

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

Waveform narrowing is an attractive framework for circuit delay verification as it can handle different delay models and component delay correlation efficiently. The method can give false negative results because it relies on local consistency techniques. We present two methods to reduce this pessimism: 1) global timing implications and necessary assignments, and 2) a case analysis procedure that finds a test vector that violates the timing check or proves that no violation is possible. Under floating-mode, global implications eliminate timing check violation without case analysis in the c1908 benchmark, while for a tighter requirement case analysis finds a test vector after only 5 backtracks.

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.

In this paper, we present a new non-intrusive built-in self test (BIST) methodology, aimed at improving testability of DSP architectures. The method utilizes the arithmetic blocks in DSP data paths to perform test pattern generation and test response compaction. Consequently, it requires virtually no area overhead and results in no performance degradation. Furthermore, it can be used for at-speed testing thereby providing a capability to detect failures that may not be detectable by conventional low speed testing

A novel highly efficient fault simulation technique targeted for circuits produced through high-level synthesis is presented. The technique combines hierarchical and functional fault simulation of commonly used building blocks that have regular structures. Comparison with gate-level simulation demonstrates the advantage of using this technique for this class of circuits.

This brief demonstrates a new built-in self test (BIST) scheme designated to improve a testability of digital decimators-commonly used building blocks in digital signal processing (DSP) environment. The proposed solution takes the advantage of operations offered by already existing functional blocks to perform basic testing functions. Thus it drastically reduces the need for an additional testing hardware as well as eliminating the performance degradation usually introduced by traditional BIST schemes. An easy to test implementation of the decimator based on a custom data-path architecture is also analyzed