The newly suggested synapse capacitor (synaptor) in this work has a cross‐point feature, enabling implementation at a feature size of 4F2. This synaptor has a gate surrounding semiconductor pillar (GSSP) structure with overturned charge injection (OCI) scheme to ensure high capacitive memory window. Sentaurus TCAD simulation tools are used to demonstrate the process feasibility and device characteristics. Two important process parameters are optimized to show the best characteristics; overlap height (Hov) and channel pillar height (Hch). An OCI‐GSSP device that has an aspect ratio of 10 and the minimal overlap height shows the highest Con/Coff over 5 in 40 nm wordline and BL pitch. It is the highest value and the smallest unit device size among the capacitive synapses that have been reported up to now. Advantages of scaled OCI‐GSSP devices are appealed through subarray circuit simulation. The subarray composed of OCI‐GSSP synaptor can calculate one vector‐matrix multiplication operation with energy under 200 fJ and column delay of 3 ns, and result in sufficient signal margin of 275 mV.

Over the past 25 years, as design rule decreased by 90%, the DRAM cell capacitance also decreased by 90%. Despite those reductions, advances in cell transistors, optimizations of sensing margin and innovative design solutions have made the development of 10nm-class DRAMs possible. This paper explores these key innovations and discusses how the continued optimization of device architecture and design solutions are essential for advancing DRAM technology beyond the 10nm era.

A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances ( C on and C off ) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 10 7 cycles and retention time of 10 4 sec.

Artificial intelligence (AI) is increasingly used to solve multi‐objective problems and reduce the turnaround times of semiconductor processes. However, only brief AI explanations are available for process/device/circuit engineers to provide holistic feedback on the manufactured results. Herein, linear/nonlinear variation decomposition (LVD/NLVD) of neural networks is demonstrated to quantitatively evaluate the influence of unit processes on the figure of merit (FoM) and co‐analyze the unit process influences with device characteristic behaviors. The NLVD can evaluate the output variation from each input of neural networks in an individual sample, although neural networks are not available in an analytic form. The NLVD is successfully verified by confirming that a) the output and summation of all decomposed output variations perfectly coincide and b) the process influences on the FoM are decomposed to 6.01–54.86% more accurately compared with those of LVD in 1Y nm node dynamic random‐access memory test vehicles with a baseline and split tests introducing high‐k metal gates with a minimum gate length of 1 A nm node for further node scaling. The approaches identify defective processes and defect mechanisms in each sample and wafer, which enhance causal analyses for individual cases in diverse fields based on regression artificial neural networks.

Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R2) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.

Stress-induced damage in a MOSFET can be cured by Joule heating, which can be produced by an intentional forward junction current ( ${I}_{\textbf {FWD}}$ ). This curing effect can be further enhanced by the simultaneous application of gate biasing, which does not influence the ${I}_{\textbf {FWD}}$ . A MOSFET was intentionally degraded by harsh hot-carrier injection (HCI) then the damage was cured and nearly returned to its pristine state. The improved self-curing effect was quantitatively verified using low-frequency noise (LFN) analyses. Self-curing by internal heat from the ${I}_{\textbf {FWD}}$ more effectively cured the HCI damage than a nonself-curing using external heat from a hot chuck.

Gate dielectric degradation caused by off-state stress (OSS) and positive-bias temperature instability (PBTI) was analyzed in terms of charge trapping inside the gate dielectric and at the interface. Under the same degree of stress voltage, the OSS damage caused more degradation of threshold voltage (V-T) than the PBTI damage. When the two stresses were alternately applied to an n-channel MOSFET, they effectively produced a leftward shift in the V-T. This was because a greater negative V-T shift was produced by the OSS and a less positive V-T shift was produced by the PBTI. By analyzing the characteristics of the gate induced drain leakage (GIDL), it was deter-mined that charge trapping inside the gate dielectric was more localized on the drain side than on the source side after OSS, but was distributed at a relatively similar level along the channel length direction after PBTI. To analyze the interface traps caused by OSS and PBTI, charge pumping (CP) measurements were conducted to map their lateral distribution along the channel direction. The PBTI-induced interface traps were found to be sym-metrically distributed on the source side and drain side, while the OSS-induced interface traps were more concentrated toward the drain side.

Low-frequency noise (LFN) characteristics under OFF-state stress (OSS), which degrade device performance, were investigated in n-channel MOSFETs. The power spectral density (PSD) was analyzed by investigating the LFN and the border traps located in the gate oxide were extracted along a depth direction perpendicular to the silicon (Si) channel surface. The holes generated by band-to-band tunneling (BTBT) in the overlap region between a drain and a gate were found to be more detrimental to device performance than channel hot-carriers created by impact ionization.

This study demonstrates a method for curing the gate dielectric of a MOSFET using Joule heat (JH) generated by forward bias current in the PN-junction in the drain-to-body (D-B) and source-to-body (SB). To accurately quantify the curing effect by the D-B JH and the SB JH, the interface trap density (Nit) of the gate dielectric was laterally profiled using a charge pumping characterization method. The curing method was applied to repair damage in the gate dielectric caused by Fowler-Nordheim (FN) and hot-carrier injection (HCI) stress. When FN stress was applied to the device, there is no difference in curing the damage by the D-B JH and the SB JH. However, when HCI stress, which asymmetrically causes more damage to the drain, was applied, the D-B JH showed better recovery than the SB JH.

The turn-around effect of drain linear current (I-dlin) with stress time in a pMOSFET in the off-state stress is investigated. The degradation rate of I-dlin increases to a maximum of 6.1% at 20 s of the stress time and then continuously decreases to 3.35% at 1000 s in the off-state stress. The turn-around effect is analyzed by comparing the degradation rates of the performance parameters (I-dlin, I-dsat, SS, and V-th) in the off -state and gate induced drain leakage (gidl) -state stress modes. The results indicate that the I-dlin turn-around effect in the off-state stress, which occurs as an effect of the negative oxide charge (Q(ox)) formation, is more significant than that of the interface trap (N-it) for short stress time (before 20 s), and the donor-like N-it formation has major effects compared to those of Q(ox) over a long stress time (after 20 s). This observation shows that the stress-induced trap generation can be investigated even if the protection diode exists and critically impacts the drain current degradation and should be seriously considered in the reliability of a DRAM circuit.

The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic randomaccess memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance (gm) and ON-state current ( ION), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized.

We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H-2) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.

To characterize electrically the effect of the Cu diffusion in TSVs, a new test pattern is proposed and its effectiveness is verified experimentally. The test pattern has a shallow n + region formed in an n-well region butted to the TSV dielectric surrounding the TSV. Through the n + /n well region, we can measure the diode and gated diode currents, the charge pumping current, and C-V to accurately analyze the effect. Our approach is demonstrated to be very useful by investigating the Cu diffusion effect in samples with two different barrier metal thicknesses.

The Vt variation and positive bias temperature instability (PBTI) of TiN/W and TiN metal buried-gate (BG) cell transistors in DRAM are characterized. The use of TiN gate shows a larger Vt variation and different PBTI behavior as compared with TiN/W gate and these are attributed to the formation of chlorine (Cl)-related trap sites during the etch-back process of metal gate. This indicates that Cl in the chemical vapor deposition (CVD) TiN gate is responsible for the phenomena.

The Vt variation of TiN-metal buried-gate (BG) cell transistors in DRAM is characterized. The use of TiN gate shows a large Vt variation and is attributed to the formation of chlorine (Cl)-related trap sites during the etch-back process of the metal gate. This indicates that the Cl component in the chemical vapor deposition (CVD) process of the TiN gate is responsible for such a phenomenon. Reduction of the Vt variation is achieved by rapid thermal annealing (RTA) after the etch-back process.

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D it). It is worthwhile to note that the D it as well as the GIDL current is a still meaning parameter to analyze the data retention time.

The effect of mechanical stress induced by shallow trench isolation (STI) slope on the data retention characteristics of DRAM is investigated and a new electrical parameter for monitoring the mechanical stress is proposed. To maintain high and uniform retention time for the reliable operation of DRAM, the STI slope should not be vertical and should be kept below 86-degree. The new electrical parameter measures the current gain of the parasitic BJT in DRAM cell and shows a strong correlation with the retention time induced by the mechanical stress.