A comprehensive ESD robustness study of 5 different Ge photodetectors in advanced Si photonic technology is presented. The measurement results disclose that the main impact on the ESD transient IV characteristics is from the contact location of the anode terminal. Still, the failure mechanisms need to be further clarified by physical failure analysis as a part of the future work.

We report on several key elements for enabling advanced compute scaling. At transistor level, as we are entering the nanosheet (NS) era, the focus lies on single-level NSFETs consisting of several vertically stacked NS per device, which can evolve into 3D stacked configurations like the so-called complementary FET (CFET) with potentially different materials/crystal orientations for the stacked channels. New device connectivity schemes are also becoming possible thanks to the trend towards using both wafer sides, started with the move of on-chip power distribution to the wafer’s backside. As devices are becoming sandwiched and accessed from levels above and below them, that also allows interesting new opportunities for transistor engineering, some examples of which will be discussed here. In parallel, from a system level’s perspective, a (r)evolution towards smart disintegration, enabling higher flexibility and hybridized technology platforms, is expected to further allow new scaling paths, also as it can help ease the introduction of new materials and device architectures.

Although not mainstream yet, Contact Charged Device Model (CDM) electrostatic discharge (ESD) testers are being used by the industry. In this paper we compare the Low-Impedance Contact CDM tester to the industry standard Field-Induced CDM tester. We test an actual IC product at wafer, bare-die and package levels.

Extremely thin wafers are an important enabler for high density nano Through Silicon Via (nTSV) in future system-technology co-optimization (STCO) scaling. Measurements and TCAD simulations indicate that reducing the wafer thickness to 0.3µm is beneficial to latch-up prevention because of lower β-gain, which is induced by the strong recombination in well-base regions.

In this work, impact of cryogenic operation temperatures on latchup in 28nm planar bulk CMOS technology is discussed for quantum computing applications. Measurement and simulation results indicate that at low temperatures the sheet well resistances experiences 60% increase. Further simulations reveal that the vertical resistance increases leading to latchup risk. However, the current gain product of the parasitic bipolar transistors reduces, and holing voltage is increased with low temperatures which can compensate the latchup risk.

The need for increased computing keeps growing at an ultra-fast speed, required to support an ever larger and wider range of applications [1]. Meanwhile, recent advances in 3D and photonic technologies are allowing new connectivity possibilities besides the typical on-chip interconnects at system-on-chip (SoC) level. This is enabling a system (r)evolution towards smart disintegration, moving away from a one-meets-all-requirements general-purpose CMOS platform, and allowing higher flexibility by separately designing and fabricating the blocks that are assembled in the final system [2]. Boosted by the novel scaling options enabled by this new approach, logic standard cell shrinkage remains at the core of the compute roadmap. Its momentum is expected to carry on by introducing new device architectures, materials, and scaling boosters such as backside (BS) power delivery (PD) [3-9]. Guided by design-technology-co-optimization (DTCO)-driven design improvements, in close interaction with the adoption of system-technology-co-optimization (STCO), the roadmap also increasingly requires EUV/high-NA EUV lithography for cost-effective, lower energy consumption, continued dimensional scaling. At transistor level, finFETs are being replaced by nanosheet (NS) FETs consisting of several vertically stacked NS per device [10,11]. Beyond that, 3D stacked CMOS, also called CFET [9,12,13], where different polarity NSFETs are folded on top of each other, appears as the ultimate scaling limit of the NS-based transistor’s family. Moreover, changes in how devices are connected are also being introduced. Moving PD to the wafer’s BS, though being a considerable disruptive technological change, is a game changer for on-chip power distribution, enabling smaller IR-drop values. This concept can be implemented in various ways, and has the potential to expand towards other functions, namely by addition of specific devices after BS processing, paving the way towards a truly functional BS [3,9,14]. Two examples of benefits brought by increased BS use are: 1) considerably more compact ESD diodes, with improved latch-up immunity, and BS contacts [9,15]; 2) lower clock latency values by moving the clock’s signal to the BS [9,16]. Furthermore, as transistors are now sandwiched and accessed from levels above and below them, this also enables interesting new opportunities for device engineering. Focusing on the highly scalable BS PD scheme wherein the transistor’s source (S) (for bottom FET in case of CFET) is directly contacted from the BS (BSC-S) (Fig.1) [7,9,17,18], while the other terminals remain connected from the wafer’s frontside, several options to optimize the BSC-S’s contact resistance can be considered. These include ways to enlarge its contact surface area and the possible addition of an extra low-temperature, low-resistivity epitaxial layer [9,19,20] prior to metallization. Fig.2 also highlights the need to account for the impact on thermal performance when selecting (BSC-S)-based device configurations and materials [7,9]. Additionally, the intrinsically asymmetric S/drain (D) access with BSC-S can also be explored to enable a simpler path to build devices with differently doped S/D [9]. This can be especially interesting for high-mobility, low-bandgap FETs to mitigate I OFF concerns while still taking advantage of their high-drivability potential. CFET using, e.g., bonding technology for the bottom/top channels and their vertical isolation’s definition can also be particularly suitable for implementing distinct channel materials (like Ge-rich for bottom PMOS) as they are in separate planes. Overall, compute systems, guided by DTCO/STCO with the embrace of the use of both wafer sides, 3D stacking and sequential technologies, can potentially be assembled in ways enabling much more versatile, hybridized platforms. This can allow not only new paths for continued compute/logic scaling, but also ease the introduction of new/alternative device architectures (and materials) as they do not need to meet all the requirements of a general-purpose platform. References [1] Y.-J. Mii et al. , VLSI 2022, 276; [2] M. G. Bardon et al. , Imec ITF World 2023; [3] J. Ryckaert et al. , EDTM 2019, 50; [4] A. Veloso et al. , VLSI 2021, TFS2-6; [5] R. Chen et al. , IEDM 2021, 498; [6] A. Veloso et al. , VLSI 2022, 284; [7] A. Veloso et al. , IEDM 2022, 563; [8] M. Shamanna et al. , VLSI 2023, T1-1; [9] A. Veloso et al. , IEDM 2023, T19-2; [10] N. Loubet et al. , VLSI 2017, 230; [11] J. Jeong et al. , VLSI 2023, T1-2; [12] J. Ryckaert et al. , IEDM 2019, 685; [13] M. Radosavljević et al. , IEDM 2021, 721; [14] J. Ryckaert, Imec ITF Japan 2022; [15] K. Serbulova et al. , VLSI 2022, 431; [16] S. K. Lim, VLSI 2023, WS3-4; [17] S. C. Song et al. , IEDM 2021, 494; [18] M. Kobrinsky et al. , VLSI 2023, TFS2-1; [19] C. Porret et al. , IEDM 2022, 807; [20] N. Breil et al. , VLSI 2023, T1-5. Figure 1

In this work, the challenge of the I/O development roadmap is discussed. Utilizing design and technology co-optimization (DTCO), a cost-effective circuit solution of a 1.8-V general-purpose I/O (GPIO) is proposed in this work. It is not only designed to have comparable performance with standard I/O cells but also better scalability adapting to the sub-3-nm gate-all-around (GAA) nanosheet (NS) technology. The proposed GPIO consists only of core transistors, so that an I/O transistor is not required. To tolerate I/O domain voltage of 1.8 V, the proposed GPIO is designed in the stacked architecture to be 3 $\times$ VDD tolerant. The proposed high-voltage tolerant level shifter with supplementary design achieves better technology scalability regarding performance. The dynamic gate bias (DGB) circuit can prevent gate-dielectric overstress in the output driver under static states. A new voltage-lowering technique has been proposed for receive mode (RX) and achieves better duty cycle and functionality of hysteresis. The functionality is demonstrated in a commercial 16-nm FinFET technology. Furthermore, the device-level reliability of stacked transistors is qualitatively evaluated by the proposed reconfigurable stacked-FET array. The circuit solution to the reliability concern induced by transient overstresses under transmit mode (TX) is proposed. In addition, the circuit-level reliability of the proposed GPIO is examined and shows comparability to the device-level measurement results. Finally, the area penalty and comparison of the conventional I/O buffer and the proposed GPIO has been analyzed, and the technology dependency of device reliability has been discussed.

Wafer-to-wafer hybrid bonding allows for the integration of different semiconductor materials and the creation of complex 3D structures, resulting in higher device density and reduced interconnect parasitic. This paper focuses on the RF performance of the interconnect in hybrid bonded devices. Specifically, we study noise coupling between 5/5μm TSVs, as well as inductive links between different metal layers and their applications for both wireless communication and non-invasive wafer testing. The study combines experimental measurements with calibrated HFSS models up to 67 GHz. ESD tests have also been conducted on hybrid-bonded inductor loops for reliability evaluations.

This work investigates HBM performance in GaN-on-SiC RF HEMTs. Forward and reverse G-S Schottky diodes are evaluated in RF multi-finger HEMTs with different widths and using inside or outside through-substrate vias (TSVs). HBM zaps on D-S HEMTs are conducted. Finally, benchmarks with GaN-on-Si HEMTs are proposed in terms of G-S Schottky diodes and D-S HEMTs.

Presentation slides for the ISTFA 2023 Tutorial session “ESD Challenges in Advanced CMOS Technologies-Designing Diode Based ESD Protection.”

In this work, the impact of buried power rail (BPR) on latch-up (LU) immunity is discussed. Measurement and simulation results indicate an increase in LU immunity by inserting BPR which brings the feature of blocking the current path. Furthermore, the differences in current gain product with different BPR biases including Vss, Vdd, -Vdd, and their difference in location, namely p-type well (PW) and n-type well (NW) are covered. The appropriate bias further increases LU immunity however the inappropriately applied voltage to the BPR lines compared to the well bias induces unexpected LU risk.

In this paper, the impact of double-sided connectivity and buried power rails (BPR) on electrostatic discharge (ESD) diodes is reported. Connection from the backside and BPRs can change ESD current path and uniformity. It also introduces parasitic capacitance and layout penalty to ESD diodes. The ESD performance is strongly dependent on layout styles. Guidelines for a better layout style of double-sided connectivity cooperating with BPRs are proposed.

Gallium Nitride (GaN) high electron mobility transistors (HEMT) exhibit 3 different types of HBM failures, namely, reverse Schottky electric field (REF) failure, 2DEG channel constant power (CP) failure and forward Schottky current crowding (CC) failure. HBM robustness of each failure can be improved by ~75% to ~200% by increasing the gate-ohmic spacing or by increasing device width. Increasing field plate length increases HBM robustness against REF by ~50%. Similarly using a back barrier helps increase HBM robustness against CP failure by ~60%.

Heterogeneous bonding technologies are an attractive way to assemble high performance computing systems today. However, ESD risks of 2.5D/3D bonding are not fully understood. To help ESD control engineers and tool manufacturers, this paper describes the 2.5D/3D bonding processes and gives practical insights into the relevant ESD process assessment steps.

In the design-technology co-optimization (DTCO) and system-technology co-optimization (STCO) scaling era, sub-μm Si substrate has been inevitable for the decent vertical connections. This work, for the first time, evaluates the ESD performance of various ESD devices, including ESD diodes and MOSFET-based ESD devices, with extremely thinned wafer thickness of 300nm and double-sided connectivity. The detriment of the wafer thinning has been assessed for these ESD devices with different key design parameters. Furthermore, the thermal dissipation of these ESD devices with active back-side (BS) contact and metals has been investigated for a possible solution to the thermal issue resulting from the extremely thinned Si substrate.

We report on devices built with the power delivery network (PDN) moved to the wafer’s backside (BS) for lower IR drop and improved routing efficiency. This concept can be implemented by differentiated schemes, some of which can be combined for 3D stacked structures such as CFET, and with Buried Power Rail (BPR) connected via scaled nTSV to BSM1 used for a first experimental demonstration. Device fabrication starts with frontside (FS) processing, after which the wafers are flipped over, bonded to carrier wafers and continued for the BS flow. Robust extreme wafer thinning has been achieved with a SiGe-Etch Stop Layer (ESL) added early on the FS, without impacting device properties. Optimized post-BS anneal(s) are shown to be effective for V T recovery (as some depassivation may occur after FS process), yielding improved mobility, DC performance, reliability and noise behavior. A scenario where the device’s source (S) is directly contacted from the BS (BSC-S) offers higher cell’s scalability potential, with stress, contact resistance, thermal (chip vs. transistor level, focus on hotspots) aspects assessed for various configurations. Its intrinsic S/D asymmetric access can also be explored to obtain low I OFF for small bandgap Ge/SiGe FETs. Further exploration work shows clear benefits for ESD diodes with BS contacts and for clock distribution implemented with (partial) BS routing, paving the way to a truly functional BS and new STCO opportunities.

Three-dimensional (3D) die-stacking has become a promising way to continue improving the integrated circuits performance. However, the risk of electrostatic discharge (ESD) during the stacking process is not yet fully understood. In this paper, we focus on understanding the electrostatics before the contact moment for the 3D stacking process. Our findings indicate that the stacking process presents a relatively low risk of ESD.

Gallium nitride (GaN)-on-Si technologies for advanced RF applications have been raising the attentions in semiconductor industries, which accompany with RF electrostatic discharge (ESD) reliability challenges. Both positive and negative ESD stress polarities are equally important to be investigated. Four scenarios of the positive and negative human body model (HBM) stresses on a gate-tied-to-source configuration (G S $_{\mathbf {\textit {MI}{S}-\textit {HE}\textit {MT}}}$ ) and a gate-tied-to-drain configuration (G $\text{D}_{\mathbf {\textit {MI}{S}-\textit {HE}\textit {MT}}}$ ) were conducted in GaN-on-Si MIS-HEMTs. A failure mechanism unveiled in the negative G S $_{\mathbf {\textit {MI}{S}-\textit {HE}\textit {MT}}}$ which is different from the constant-power 2DEG failure mechanism in the typical positive G S $_{\mathbf {\textit {MI}{S}-\textit {HE}\textit {MT}}}$ , was demonstrated by the measured HBM transient I-V characteristics and the subsequent DC I-V traces. The specific ON-state failure mechanism is related to the constant-voltage gate dielectric failures, resulting from a unique HBM discharge mechanism without the existence of depletion region in the 2DEG channel. This causes the degradation of the HBM failure voltages on the devices. Thus, the lower HBM failure powers are required to destroy the gate dielectric layer, as compared to the high failure powers to induce the 2DEG burnouts.

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length ( ${L}_{g}$ ) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance.