A System on Chip (SoC) solution for ultra-wideband (UWB) and mm-wave MIMO radar applications is presented. The RFIC is implemented in a standard CMOS 65 nm process, comprising 24 transmit-receive modules for UWB along with 48 transmit-receive modules for mm-wave frequencies. Targeting radar applications, the signal generation architecture supports a variety of waveforms. The receive side includes multichannel digitization, memories and DSP processor for radar signal processing. The SoC family has several variants, supporting the 76-81 GHz band for automotive industry and a 57-71 GHz band for smart home applications. The die area is 83 mm 2 and it is packaged in a flip-chip BGA package.

The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task. The frequency modulation dynamics are analyzed for this architecture. The results are employed to implement a SiGe BiCMOS fully integrated 75-83 GHz frequency-modulated continuous-wave synthesizer. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism together with the dual-loop PLL architecture provides low loop bandwidth variation over the whole output frequency range, -97 dBc/Hz phase noise at 1-MHz offset, and maximal modulation rate of 100 GHz/ms.

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<;0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A linear RF to IF downconversion and IF to RF upconversion mixers for 60-GHz transceivers were implemented in 0.13-mu m SiGe technology. The mixers were implemented using a mixing core only topology for enhanced linearity, with no local oscillator (LO) buffers and a transformer-based matching network for IF frequencies. The downconversion mixer at full attenuation shows a minimum of 10-dBm IIP3 and maximum measured loss of 6.5 dB within the entire 57-66 GHz frequency band. Without attenuation, the conversion gain is above 4 dB, with better than 2-dBm IIP3 and a noise figure maximum value of 14 dB within the band. The transmit mixer exhibits less than 2.5-dB conversion loss, better than 7.5-dBm OIP3 with minimal temperature variations. For improved LO to RF isolation, separated dc bias control is used in the mixing devices providing over 46-dBc LO suppression within the band. The mixers occupy only 0.47 and 0.22 mm(2) consuming 56 mW for downconversion mixer with IF amplifier and 27 mW for upconversion mixer.

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1-3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <;1° RMS error and <;5° phase steps for precise beam control.

We present a SiGe BiCMOS fully integrated 75-83 GHz FMCW synthesizer for automotive radar applications. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism was incorporated in a dual path PLL, providing low loop bandwidth variation over the whole output frequency range, -97 dBc/Hz phase noise at 1 MHz offset and maximum chirp rate of 100 GHz/mSec.

A fully integrated 60 GHz transmitter in 130 nm BiCMOS SiGe technology for outdoor applications is presented. The transmitter covers the entire 57-66 GHz band supporting a record data rate of 16.2 Gbps at 6 dBm output power, 512 QAM with an EVM of -34 dB. The single ended saturated power, OP1dB, and OIP3 are above 18 dBm, 16 dBm and 23 dBm respectively. The transmitter meets the most stringent ETSI emission mask for point-to-point communication at class6LB, 500 MHz bandwidth with an output noise floor below -133 dBm/Hz. The area of the transmitter is 15 mm2 and it consumes 1.2 W.

Phase shifters are key components in phased array systems. A low loss and low loss variations SiGe differential phase shifter for the Ka-band is described. This bidirectional differential reflection type phase shifter (RTPS) design employs a novel diagonal configuration for the coupler and it is controlled by a single voltage node. The measured results show state of the art insertion loss of 5±1 dB, phase tuning range larger than 180 degrees, for a frequency range of 26.5 GHz to 32.8 GHz (21%). At 30 GHz, the phase shifter exhibits insertion loss of 4.8 dB, loss variation of ±0.4 dB, and more than 206 degrees of phase shift range. The RTPS was fabricated in a standard BiCMOS SiGe process and occupies 0.64 mm2 die area.

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the 81-86 GHz band was designed and fabricated in 0.13 μm SiGe technology. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chip achieves maximum gain of 73 dB, 6 dB noise figure, better than -12 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chip includes a power amplifier (PA), image-reject driver, variable RF attenuators, IF-to-RF upconverting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 16.6 dBm, P sat of 18.8 dBm on a single-ended output and consumes 1.8 W.

A compact frequency octupler designed for upper and lower E-band transceivers is implemented in IBM 0.13μm SiGe technology. Three frequency doubler stages are used with harmonic rejection conducted at the first two doublers for wide band spectral purity. With a 0 dBm input power, the frequency octupler reaches above 7.5 dBm output power between 56 GHz to 84 GHz with a peak output power of 13.5 dBm. All even harmonics: 2nd, 4th, 6th, 10th, are suppressed by more than 40 dBc across the frequency band. Moreover, the 6th and 10th harmonics are suppressed by over 40 dBc at temperatures between -40°C to 85°C. The circuit enables an extra input option of a frequency quadrupler and occupies 1.23×1.1 mm2 and consumes 152 mA from a 2.7 V supply.

This paper presents a K u band G m boosted Colpitts VCO designed in IBM 0.13μm SiGe BiCMOS8hp technology for E-Band and V-band backhaul transceivers. The VCO achieves 23.3% tuning range, covering 15.2 - 19.2 GHz while maintaining low phase noise. Measured phase noise at 10 MHz is lower than -133 dBc/Hz at 25°C. The VCO shows robust behaviour to temperature variations, with a measured frequency drift of less than 15 ppm/°C. The power consumption is 51.4mW and calculated FOM is -183.5 dBc/Hz.

A compact frequency tripler designed for 60 GHz transceivers is implemented in 0.13μm SiGe technology. The common emitter class-A frequency tripler uses a transformer based output filter combined with transmission lines to achieve high harmonic suppression. The frequency tripler followed by an amplifier covers a 3dB frequency range between 48 GHz to 58 GHz with a peak output power of 9.5 dBm. Fundamental frequency is suppressed by more than 28 dBc and the 4 th harmonic is suppressed by more than 35 dBc between -40°C to 85°C degrees across the frequency band. The tripler design occupies only 390 μm × 495 μm and consumes 62 mW from a 2.7 V supply, the design followed by an amplifier occupies 960 μm × 980 μm raising the DC consumption to 220 mW.

This paper presents a Ku band sub-integer frequency synthesizer designed in IBM 0.13um SiGe BiCMOS8hp for E-band backhaul transceivers. To improve phase noise a Gm boosted Colpitts topology was used together with a 4 bit capacitor bank for wide tuning range. Utilizing a sub-integer phase rotating divider the synthesizer realizes 132 channels with a 27.78 MHz resolution, covering 15.583 - 19.11 when using a 55.56 MHz reference. Phase noise is lower than -133 dBc/Hz at 10MHz offset, while reference and sub-integer spurs are lower than -56dBc. The synthesizer is robust to temperature variation within -400C to 85°C.

This paper describes circuit design and measurement results of a multi-tanh bipolar rms power detector (PD) for applications in E band (65-86 GHz) frequency range. The PD is designed and fabricated in IBM 0.13um SiGe technology. In the matched frequency range, the measured input dynamic range is over 40 dB, withstanding an input power of 17dBm, with an overall sensitivity of 27.5 mV/dB. The output voltage response is nearly frequency-independent, varying by less than 1.5 dB for a given input RF power, as the RF frequency is swept across the operating frequency range. Static power consumption is 12mW from a 2.7V supply.

A high output 1dB compression up-conversion mixer for the entire E band frequency range, 71-76 GHz and 81-86 GHz, is designed and fabricated in IBM 0.13 μm SiGe technology. The mixer is comprised of a double balanced Gilbert cell and a multi-tanh three transistor hybrid transconductance stage, used to enhance the mixer linearity. The conversion gain and output 1dB compression are 3.9dB and +1dBm, respectively at 71GHz and vary within 3dB and 4dB respectively over the entire 15GHz range. LO leakage is less then -30dB and noise figure is under 9dB. The circuit consumes 80mW from a 2.7V supply.

A compact ×2 frequency multiplier covering all ku band is implemented in IBM 0.13μm SiGe technology. The transformer coupled circuit uses a common base configuration working in B- class mode and utilizes transmission lines properties to achieve harmonic suppression. The doubler covers a 3dB frequency range between 12.2 GHz to 20.4 GHz with a saturated output power above 9 dBm. The fundamental frequency is suppressed by over 27 dBc and the 4th harmonic is suppressed by more than 25 dBc across frequency band. The core design occupies only 550 μm × 620 μm and consumes 37 mW from a 2.7 V supply.

A distributed differential frequency tripler covering the 30-90 GHz range is implemented in IBM 0.13-μm SiGe technology. The distributed design utilizes a right-handed input and a left-handed output synthesized transmission lines to overcome the challenging fundamental rejection. Six cascode stages in deep saturation act as frequency generators connected in a differential configuration for even harmonic suppression. Operation is demonstrated for 30 to 90 GHz output range with minimum spur rejection of better than 10 dBc between 43 to 79 GHz. Output power varies between -8.3 dBm at 72 GHz and reaches -0.8 dBm at 45 GHz. The core circuit occupies only 0.16 mm2 and draws 151 mA from a 2.4 V supply.

An IF to RF up-conversion mixer for the entire E-BAND 71-76 GHz and 81-86 GHz frequency range was designed and fabricated in IBM 0.12 μm SiGe technology. The Mixer comprises of a double balanced Gilbert-cell with a degeneration inductor in the amplifying stage for increased linearity. The mixer exhibits conversion gain higher than -2 dB, output compression point above -7 dBm, and LO leakage less than -30 dB. The core mixer area is 0.37 mm 2 and consumes 140 mW from a 2.7 V power supply.