The first CMOS current reference with a measured temperature coefficient across cryogenic temperatures is reported. Implemented in a 14nm FinFET technology, occupying 0.14mm2, and drawing 38uA from a 1.4V supply, the reference uses mutual compensation between a MOSFET gate-source voltage and thin-film resistance—a circuit technique that improves as cryogenic temperatures are approached—to achieve a temperature coefficient of 128ppm/K over 5.6-100K, as averaged over 5 dice from 3 wafers. The cryogenic supply sensitivity, at 0.06%/V, is 6x lower than the lowest reported among cryo-CMOS references, either current or voltage. Finally, cryogenic low-frequency noise is measured for the first time among cryo-CMOS references, either current or voltage.

Experiments with superconducting quantum processors have successfully demonstrated the basic functions needed for quantum computation and evidence of utility, albeit without a sizable array of error-corrected qubits. The realization of the full potential of quantum computing centers on achieving large scale fault-tolerant quantum computers. Science, engineering and industry advances are needed to robustly generate, sustain, and efficiently manipulate an exponentially large computational (Hilbert) space as well as supply the number and quality components needed for such a scaled system. In this article, we suggest critical areas of quantum system and ecosystem development, with respect to the handling and transmission of quantum information within and out of a cryogenic environment, that would accelerate the development of quantum computers based on superconducting circuits.

Quantum computers offer the promise of accelerated solutions for types of problems that are computationally unaffordable or intractable for classical computers, such as the simulation of quantum mechanics itself, quantum chemistry, and mathematical challenges like factoring large numbers. However, the relatively high error rate per quantum computing operation in the systems of today and of those expected to be developed in the future remains a key obstacle. To address this challenge, quantum error correction (QEC), which enables the creation of error-corrected (logical) qubits from a collection of physical qubits, is required. Depending on the choice of QEC code, hundreds of physical qubits may be required to implement a single logical qubit. As a result, the race to the creation of quantum computing systems capable of outperforming classical computing systems is largely a race to create quantum computers at the scale needed to support QEC. The criticality of scaling is evident in the quantum computing roadmaps produced by major research labs in this field, such as the one from IBM shown in Fig. 1. Starting from systems with only a few physical qubits a few years ago, the roadmap projects quantum computers with around 100,000 physical qubits and thousands of logical qubits by 2033 or so.

Cryogenic CMOS control and readout electronics for quantum computing using superconducting qubits offers several potential advantages versus the use of room temperature electronics, including reduced wiring and lower cost per control channel. The development and practical implementation of such electronics at a mass-production scale for systems with tens of thousands of channels, however, requires circuit characterization in the target cryogenic use environment and with interfaces as close as possible to those that will be used in a real quantum machine. The cryogenic use environment and interfaces for test are usually far from the almost ideal conditions that can be achieved in a regular cryogenic probe station. In this paper, we describe a new testbed for the characterization of CMOS circuits at cryogenic temperatures that solves some of these problems.

We report a new approach to building an ASIC-style superconducting SFQ logic cell library for the 8-layer 0.35 μm Niobium SFQ5ee process from MIT LL. The developed library layout template supports XY routing with Passive Transmission Lines (PTLs) and targets conventional Place-and-Route assembly for the design of VLSI Random Logic Macros (RLMs). The designed library gates are based on clockless Dynamic SFQ (DSFQ) logic which allows one to directly implement deep combinational logic clouds. The full library gates communicate only via an XY PTL routing plane, while internally they are assembled from smaller self-contained subgates, connected via inductors and placed in one template row. We report test results for two chips that independently verify library subgate assemblies that are used to build DSFQ logic gates as well as active PTL interconnect; on-chip testbenches provide low-speed and high-speed (GHz) test modes. We have achieved low-speed and high-speed functionality of both the DSFQ logic gates (AND, OR, and AO21) and active interconnect circuitry (transmitters Tx and receivers Rx) used for communicating SFQ signals over 700 μm PTLs and short (∼50 μm) series inductor-resistor (LR) connections. The measured speed of the OR and AND logic circuits exceeded 10 GHz, while the speed for PTLs and LR connections was more than 10 and 30 GHz, respectively.

Today’s quantum computing systems rely on commercial electronics operating at room temperature in order to perform control and readout operations for qubits [1] –[6]. The qubits operate at cryogenic temperatures; the signals that support control and readout of qubits therefore traverse multiple temperature stages in a dilution refrigerator to enable interaction with the qubits of a quantum computer. For many of the most advanced quantum computers built to date, the control of each individual qubit demands application of a radiofrequency pulse that is precisely calibrated in frequency, amplitude, and phase. Oubit readout demands the amplification of very low amplitude signals that are then post-processed to categorize the state of the qubit being measured. Oubit control electronics are implemented using arbitrary waveform generators (AWGs) of various types. The scalability of such systems is challenged by the need to scale the number of qubit control electronics units linearly with the number of qubits in the system. One approach to mitigating this challenge that is under active exploration is the use of multi-channel AWGs (tailored to the requirements of qubit control) that operate at the 4K stage of a quantum computing system [7] –[10]. Oubit readout electronics are typically implemented using multiple stages of amplification and then DSP-based readout performed at room temperature. In today’s systems, while readout electronics benefits from multiplexing of the readout signals (enabling a single cascade of moderately wideband amplifiers to support the delivery of multiple readout signals to the room-temperature electronics), again, the scalability of this approach is challenged much as is the case with control electronics. One approach to mitigating the readout challenge is the expanded use of cryogenic electronics in the readout chain. Success in the implementation of cryogenic control and readout solutions depends critically on multiple CMOS sub-components; in this paper we focus on SRAM and low noise amplifiers (LNAs). Note that SRAM is critical for both control and readout applications as a mixed-signal solution involving the combination of a custom processor and analog elements is highly desirable in both cases. Further, while the LNA is directly used as an element in the readout chain, a deep assessment of LNA performance and opportunities strongly benefits overall understanding of achievable noise performance in CMOS technologies at cryogenic temperatures and is therefore impoitant in both control and readout contexts.

A 5.9-8.4GHz LNA intended for use at cryogenic temperatures was implemented in a 14nm FinFET CMOS technology. At 4.1 K, peak LNA gain of 13.4dB is measured at 7.1GHz, with a 3dB bandwidth of 2.5GHz and power consumption of 2.1mW. Also, at 4.1K, measured noise figure from 6 to 8GHz is 0.53-0.57dB and the measured noise temperature is 37.6-41K; power consumption in this set of measurements was 2.57mW.

8T SRAM, using domino read, is preferred for small-size and high-performance arrays [1]. Ripple domino circuitry relies on rail-to-rail readout, which forces a trade off between performance and the number of 8T cells on a local read bit line (RBL). To support larger array sizes, without sacrificing performance, arrays are segmented, and several segments are stitched to form the full array. Each segment requires local evaluation circuitry to connect local BL to global BLs. This local circuitry, along with the required layout fencing of each segment results in poor array efficiency.

8T SRAM, using domino read, is preferred for small-size and high-performance arrays [1]. Ripple domino circuitry relies on rail-to-rail readout, which forces a trade off between performance and the number of 8T cells on a local read bit line (RBL). To support larger array sizes, without sacrificing performance, arrays are segmented, and several segments are stitched to form the full array. Each segment requires local evaluation circuitry to connect local BL to global BLs. This local circuitry, along with the required layout fencing of each segment results in poor array efficiency.

Blockchain technology can increase visibility in supply-chain transactions and lead to more accurate tracing of goods as well as provide evidence of whether a product is authentic or not. A shared, distributed ledger or blockchain alone, however, does not guarantee correct and trustworthy supply-chain traceability. We argue that blockchain technology (and any other digital traceability solution) must be enhanced with methods to "anchor" physical objects into information technology, Internet-of-Things and blockchain systems. Only when trust from the digital domain is extended to the physical domain can the movement of goods be accurately traced (e.g., for callbacks and provenance) and product authenticity determined. In this paper, we introduce the concept of crypto anchors, propose a classification and system architecture, and give implementation examples for different use cases and industries.

In this article, we present a low-power, small form-factor, 60-GHz packaged radio featuring broad beam coverage. We increase angular coverage by beam switching between two orthogonally pointed low directivity beams that are created using two different antennas integrated in package. The resulting wide angular coverage of the radio makes radio links robust to movement and rotation; this improvement overcomes a key challenge for millimeter-wave (mmWave) deployment in portable electronics. We incorporate a 3.2 mm x 3.2 mm 32-nm CMOS radio integrated circuit (IC) in the package for radio functions. The IC includes TX and RX RF front ends, up- and down-conversion mixers, TX and RX analog baseband circuits, a common PLL, TX and RX LO chains, and ADCs and a micro-controller for built-in self-test (BIST). The IC is flip-chip packaged on a four-layer organic package comprising two TX antennas and two RX antennas. In board-level over-the-air measurements of the half-duplex packaged radio, 17.1-dBm effective isotropic radiated power (EIRP) and 6.1-dB noise figure are achieved in the TX and RX modes respectively, with power consumption below 250 mW in either mode. We characterized the radio over the air using 802.11ad waveforms; the radio is 802.11ad compliant in both TX and RX modes at data rates up to the maximum 802.11ad PHY rate of 4.62 Gb/s (raw data rate >7 Gb/s) with a TX EVM < -22 dB and RX sensitivity < -54 dBm. To measure angular coverage, we characterized 802.11ad compliance in 3-D over 3 pi steradians in first-of-a-kind measurements. The radio maintains 802.11ad compliance over 2.9 pi steradians solid angle.

Advances in artificial intelligence are already changing how computing systems interact with users and interact with their environments, with further dramatic changes on the horizon. In this context, machine learning and inference operations have become a critically important computational workload, and the importance of this workload will continue to increase. Today, GPU-, CPU-, and FPGA-based engines dominate the compute landscape for learning and for inference, but the exploration of alternative, enhanced, or complementary compute capability in this problem space is an active and growing research area. In this short course, we will provide a framework for understanding some of the computational challenges in machine learning and inference and discuss emerging technical approaches aimed at meeting those challenges.

Initial High Performance Hybrid PLL Implementation Key results A 28GHz, low noise hybrid PLL drawing 31mW from 1V demonstrated in 32nm CMOS Compact, digital friendly implementation comparable to that of digital PLL achieved Linear phase response and spurious spectral content similar to that of all analog PLL achieved Challenges Integral path redundant numbering implementation still problematic Does not really exploit opportunities presented by hybrid architecture.

This paper presents a technique for minimizing the phase noise of a CMOS PLL's oscillator. An integrated state-machine implements a gradient descent optimization algorithm to find the VCO bias voltage with the minimum frequency sensitivity to the bias voltage. This suppresses noise up-conversion within the oscillator for a key class of noise sources. The scheme is demonstrated in two separate PLLs. In a 45nm SOI CMOS 13.5-to-16.5 GHz PLL the phase noise is reduced from -90 to -103 dBc/Hz at 1MHz offset measured from a 15.5GHz carrier. In a 32nm SOI CMOS 17.5GHz-to-21 GHz, the phase noise is reduced from -78.8 to -84.2 at 100kHz offset from an 18.1GHz carrier.

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<;0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.