In this article, we propose for the first time a Gerich GeSbTe stack targeting a segregationtolerant phasechange memory (PCM) device ensuring hightemperature data retention (HTDR). We cointegrated an optimized GeN underlayer (GeN UL) with a Gerich GeSbTe material that is known to trigger phase segregation at temperatures compatible with the backendofline (BEOL) thermal budget. A channel inside the GeN layer is reliably created after the low-voltage initialization step, reducing the active volume rather independently of the cell’s critical dimension. Using statistical results from 4-kb arrays, we demonstrate a 40% programming current reduction with respect to devices without underlayer. Moreover, we present a reduced drift of the low resistance “SET” state, known to affect Ge-rich PCM alloys, and HDTR up to 250. Based on TEM/EDX analyses and TCAD simulations, we show how the combination of a reliable initialization step and the specific properties of our stack led to an innovative Ge/Sbrich GeSbTe alloy featuring promising performances.

In this article, we present the structural investigation by Raman spectroscopy of GeSbSeN ovonic threshold switching (OTS) material once integrated in selector devices featuring a top electrode based on a transparent and conductive indium tin oxide layer. The devices are characterized by standard electrical protocols, and the structural evolution of the material is investigated after several switching operations. The results are correlated with the spectra obtained from blanket samples annealed at increasing temperature and are supported by XRD and TEM analyses. We establish a link between the evolution of the material structure with the annealing process and the device behavior along cycling, bringing important advancement in the understanding of the switching mechanism and of the origin of the failure in OTS devices.

This work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier consists of a 28nm FDSOI industrial wafer with 4 metal lines. A bevel contamination wrap module allows the return of the wafer to Front End Of Line (FEOL) environment required for achieving high performance top FET Si CMOS processing. Additionally the doped poly-Si ground plane introduced enables top FET dynamic back-biasing and effective DC and HF isolation with underlying metal lines. Finally, this 3DSI platform demonstrates functional top, bottom, and 3D ring oscillators as well as a pixel with single exposure flicker-free High Dynamic Range capability obtained thanks to the stacking of an additional circuit over a bottom 3T-pixel.

In this paper, we present an innovative Multilayer SeAsGeSi-based Ovonic Threshold Switching (OTS) Selector targeting high reliability for Crossbar arrays. We compare our Multilayer (ML) OTS with SeAsGeSi-based bulk alloy (SAGS). We demonstrate the high thermal stability of the ML stack against the Back-End-of-Line (BEOL) thermal budget as well as the reduction of the device-to-device variability and reliable switching operations up to 300°C. We study by Raman and FTIR spectroscopy the integrity of the ML OTS material after an annealing of 3 hours at 400° C. SeAsGeSi Multilayer OTS delays crystallization mechanism along cycling. We finally report the successful co-integration of our ML with Phase-Change Memory technology.

A2RAM devices are fabricated using an adaptation of Si-Nanowire process flow. They include a Si-SiGe heterostructure to improve memory performance. Even the device structure is not exactly what we expect, we succeed to evidence 1T-DRAM programming.

Scaling of planar HfO2-based ferroelectric capacitors is investigated experimentally by varying the capacitor area within five orders of magnitude, under the scope of a limited thermal budget for crystallization. Both Hf0.5Zr0.5O2 (HZO) and Si-doped HfO2 (HSO)-based metal/ferroelectric/metal capacitors with a 10 nm dielectric film thickness and TiN electrodes are demonstrated to be ferroelectric when integrated in a back-end of line (BEOL) of 130 nm CMOS technology, with a maximum thermal budget below 500 °C. When the area of the ferroelectric capacitors is scaled down from 7850 μm2 to 0.28 μm2, no degradation of the remanent polarization (2·PR > 10 μC/cm2 for HSO, > 30 μC/cm2 for HZO) or of the switching kinetics (down to 100 ns at 3 V) is observed. Significant improvement of the field cycling endurance is demonstrated upon area scaling, consistent with the reduction of the total number of defects when devices are shrunk. The results pave the way for future BEOL demonstrations in 130 nm and more advanced nodes with record endurance similar to perovskite ferroelectrics.

OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (<; = 40nm), thanks mainly to its low manufacturing cost. To scale the bitcell, both the OxRAM and the selector device must be taken into account. In this paper we first show how the OxRAM reliability is impacted by scaling down to 30nm in diameter, focusing on the forming voltage, BER and data retention on a large statistics (4kbit arrays). Several strategies are provided to reduce the BER leading to a projected 10 -6 BER result. We then illustrate how thin gate oxide transistors (GO1/SG) can meet the OxRAM high voltage requirement as the memory bit approaches 100nm diameter, and we demonstrate an OxRAM (120nm) co-integration with FDSOI transistors with remarkably good performance (endurance up to 10 7 cycles on single bit). Eventually we illustrate a design example of OxRAM embedded solution in 40nm, 32Mb+ECC, featuring a 0.120μm 2 bitcell and a 170nm OxRAM cell.

This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raised source drain epitaxy) that were considered as potential showstoppers for this technology have shown decisive progress very recently.

We demonstrate successful scalability of conventional 100μm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40μC/cm 2 , endurance > 10 11 cycles, switching speeds <; 100ns, operating voltages <; 4V, and data retention at 125°C. Presented results pave the way to <; 10fJ/bit ultra-low power FeRAM for IoT applications.

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. TTOP=500 ° C) in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

This paper presents an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> based resistive switching memory (RRAM) in series with a GeSe-based Ovonic Threshold Switching (OTS) selector. Detailed investigation of the main memory operations, forming, set, reset and read is presented for the first time to our knowledge. An innovative reading strategy is proposed. The selector switching is performed only if the RRAM cell is in the Low Resistive State (LRS), while the reading of the High Resistive State (HRS) is performed without switching the OTS selector, preventing disruptive reading when the RRAM cell is in HRS. Up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> read cycles have been demonstrated with a stable memory window of one decade and a stable OTS OFF state.

In this work it is shown that laser annealing can be used for electrical activation of phosphorus implanted in extremely thin SOI structures. We characterized crystallinity, surface morphology, dopant diffusion and activation as a function of the laser energy density. It is evidenced that pulsed laser annealing (wavelength: 308 nm and pulse duration: 160 ns) allows the perfect crystal recovery of the implanted silicon layers. An optimum was found for a fluence (0.85 J/cm(2) for the blanket SOI wafers used here) for which a perfect mono-crystalline SOI layer is obtained. Moreover, sheet resistance evolution shows that very high activation rates, comparable to those obtained by rapid thermal processing or solid phase epitaxial regrowth, can be achieved. The impact of multi-pulse (2 or 5 cumulated pulses) annealing as well as the use of shorter pulses (80 ns) is investigated.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF 2 ). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.

Abstract For the first time the thermal stability of ULK/Copper and ULK/W interconnections is evaluated through morphological and electrical characterization for a 28nm design rules technology. No resistance and lateral capacitance degradation are observed for copper and W interconnections up to 500°C 2h and 550°C 5h respectively. Moreover in the case of copper interconnections, for which devices have been integrated, the functionality is fully preserved.

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

In this paper we present the impact of Sb doping of the GeS2 electrolyte in W/GeS2/Ag based conductive bridge random access memory (CBRAM) on the memory performance. In particular, the CBRAM resistance window, R-ON and R-OFF values versus programming current, power consumption and reliability are analyzed in depth.We demonstrated that the Sb concentration governs the optimal operating conditions. In particular, high Sb doping allows low programming current operation (suitable for low power applications), while low Sb content improves the R-OFF/R-ON ratio (needed in particular for nonvolatile field-programmable gate array applications). Finally, we observed that the high temperature retention could be improved by increasing the Sb doping. This result was interpreted by means of ab initio calculations, indicating that Sb reduces the dissolution rate of the Ag-based conductive filament in the electrolyte. (C) 2014 Elsevier B.V. All rights reserved.