We have proposed guiding principle of material selection of electrode/dielectric combination for MIM DRAM capacitors by theoretically taking the tunneling barrier height into account. Accordingly, we found that phase-controlled HfO2 (HfAlO) with TiN electrode is promising. TiN/HfAlO/TiN MIM capacitors with an ultra-thin Al2O3 on the bottom TiN electrode were fabricated and an EOT of 0.7 nm with a leakage current of 80 nA/cm2 was successfully achieved.

We have systematically investigated the V FB shift in the case of the stacked bi-layer high-k dielectrics with paying attention to the high-k/IL-SiO 2 interface. We demonstrate for the first time that V FB shifts are determined predominantly by the high-k/IL-SiO 2 interface, while the gate/high-k interface plays little role.

We have quantitatively investigated effective work function (Phim,eff) shift, and experimentally demonstrated that high-k/SiO2 dipole and Si-based gate/high-k contribution are critically important for understanding anomalous VFB shift. Furthermore, we have also found that annealing of metal/high-k gate stack in the reduction ambient induces another dipole formation at the high-k/Si02 interface. Finally, by using the AI2O3 and Y2O3 layer as a bottom high-k, the symmetric VTH CMOS is successfully achieved with a single metal gate electrode.

We have successfully fabricated a 0.5 nm FUSI-NiSi/ HfO2 HfSiOx/ Si gate stack structure with the gate-first process. The HfSiOx interfacial layer was formed by the cycle-by-cycle deposition and annealing process, followed by the in-situ layer-by-layer deposition and annealing for HfO2 growth. The gate leakage current of ~ 10 A/cm at Vfb - 1.0 V and the effective electron mobilityof 120 cm2/Vs at 0.8 MV/cm were obtained for n-MOSFET with EOT = 0.49 nm.

We have experimentally found two different mechanisms characterizing effective work function (Phim,eff) of a gate electrode on Hf-based high-k dielectrics. Interface dipoles induce both positive and negative Phim,eff shifts. The positive shift is almost independent of gate electrode materials, while the negative one is sensitive to Si composition of the gate electrode. Surface densities of the dipoles are estimated to be the order of 1014 cm-2. By making the most of two types of interface dipoles, we can expand a tunability of Phim,eff of gate electrodes on high-k (Phim,high-k)

Threshold voltage (V/sub th/) tuning by controlling Fermi-level pinning (FLP) position on HfAlO/sub x/(N) high-k dielectrics is demonstrated for CMOSFETs. Two kinds of methods for the effective work function tuning have been proposed. One is to control the Al concentration ([Al]) in the top interface of HfAlO/sub x/(N) to modulate the FLP position. The other is the doping into the PtSi/sub x<1.0/ (partial silicide: PASI) gates on HfAlO/sub x/(N) dielectrics. Symmetrical V/sub th/ values are obtained for the cases of poly-Si gate and FUSI (foil silicide)-NiSi gate n- and p-MOSFETs when the Al concentration is controlled in HfAlO/sub x/(N).

The dielectric breakdown mechanism of HfAlOx/SiO2 stacked gate dielectrics has been studied. Under the positive gate stress, validity of the anode hole injection model has been experimentally confirmed for the first time, while the cathode electron injection model is valid under the negative gate stress. Consolidating these mechanisms, the generated subordinate carrier injection (GSCI) model has been proposed for gate dielectrics including the conventional SiO2.

We investigate an origin of the Fermi-level pinning at the gate electrode/HfO/sub x/(N) interface, and propose a new technology for tuning the work function with a partial silicidation of Pt on HfO/sub x/ (N). It is clearly shown that the effective work functions (/spl Phi/ /sub m,eff/) of fully silicided (FUSI) NiSi and PtSi on HfO/sub x/(N) are rigidly fixed due to the Fermi-level pinning, and that the impurity doping does not help changing /spl Phi/ /sub m,eff/ at all. The large flatband voltage (VFB) shifts of FUSI PtSi MOSFETs have been observed irrespective of Si deposition processes. On the basis of these new findings, nMOSFET with pinned n+poly-Si and pMOSFET with partially pinned PtSi on HfO/sub x/ (N) for a balanced CMOS have been proposed, and both of them have shown good electrical properties. Furthermore, it is experimentally discussed that the control of the Si atom content at the PtSi/sub x//HfO/sub 2/ interface is a key factor to relax the pinning effect. The partial silicidation technology will be a most feasible method for advanced metal gate CMOS.