Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.

2008 International Conference on Solid State Devices and Materials,Vt Variation Suppressed Al2O3-Capped HfO2 Gate Dielectrics for Low Vt pMISFETs with High-k/Metal Gate Stacks

We clarified the impact of the fifth material incorporation into HfSiON technology for Vth control on the reliability of high-k/metal gate stacks CMOSFETs. HfMgSiON is remarkably effective for suppressing electron traps, giving rise to a dramatic PBTI lifetime improvement for nMOSFETs. With pMOSFETs, Al incorporation is effective for the thermal deactivation of hole traps, resulting in NBTI lifetime improvement. We have established the guidelines of material selection to be incorporated into HfSiON for reliability improvement for nMOS and pMOS individually.

A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-R s (sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (~10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.

The motions of particles are calculated in 3D structure to evaluate potential fluctuation. The results of homogeneous and thermal equilibrium systems are in good agreement with theoretical results. In 3D MOSFET, the potential fluctuation extends towards the depletion layer and deviation of the amplitude from theoretical value is observed and ascribed to hot electron energy distribution, so the conventional plasmon scattering model should be modified in non-uniform and non-equilibrium carrier distribution.

We have clarified the impact on reliability of La incorporation into the HfSiON gate dielectrics nMOSFETs (PBTI, TDDB). Although La incorporation is effective for pre-existing defect suppression, stress induced defect generation is more sensitive to stress voltage and temperature. This is caused by the elevation of the energy level of oxygen vacancy and high ionicity of La-O bond. The origin of defects is thought to be oxygen vacancy related defects, generated under positive stress and they are common to PBTI and TDDB degradation.

2007 International Conference on Solid State Devices and Materials,Suppression of Gate-Edge Metamorphoses of Metal/High-k Gate Stack by Low-Temperature, Cl-Free SiN Offset Spacer and its Impact on Scaled MOSFETs

The gate-edge properties of a metal/high-k gate stack are of crucial importance, but they have not been quantitatively investigated. In this paper, we have proposed a new method for extracting the local workfunction of the gate electrode by using a sideways overturned stack. We revealed that the TaSiN workfunction on their 10-nm long gate-edges shifted for 0.1 eV after a 1000 °C annealing. Based on these parameters, we simulated the impact of the gate-edge metamorphoses (GEM) and found that GEM increased the threshold voltage for scaled devices with a 60-nm long or shorter gate without suppressing a short-channel effect.

We have proposed a single metal/dual high-k (SMDH), low-Vth gate stack for aggressively scaled CMISFETs. The Vth is controlled by MgO- and Al2O3-containing high-k for n and pMISFETs, respectively. The gate profile can be more easily controlled by taking advantage of a common W/TiN gate stack on both high-k's. We have successfully obtained 0.21 and -0.33 V of Vth for a 1-mum long n and pMISFET by the proposed SMDH gate stacks. We also found that MgO suppresses PBTI and that it enhances electron mobility.

In this paper, the authors propose novel thin-body SOI FETs with NiSi-cladding. NiSi-cladding is fabricated after the formation of the sacrificing Si layer, and hence the Si consumption in SOI layer is minimized. It is found that NiSi cladding provides compressive strain in pFETs, which causes one order of magnitude decrease in pFET's off-current. In addition to the effect of NiSi-cladding, the influence of HfSiON gate dielectric on the floating-body effect (FBE) in thin-body SOI pFETs is focused upon

Self-organized (111) faceted NiSi 2 source and drain structure with segregated dopants in the NiSi 2 /Si interfaces has been proposed for aggressively scaled SOI MOSFETs. The advantages of this source and drain structure are a superior short-channel effect (SCE) immunity and a very small parasitic resistance. The SCE is suppressed by a trapezoidal shape of the channel and by a small variation in the channel length that is obtained thanks to the epitaxial growth of NiSi 2 on Si. The significant effects of the channel shape and the variation-free channel length are also confirmed by the numerical simulation. Owing to the low-temperature annealing at 600degC for NiSi 2 formation and dopants activation, wider selections of gate metal and high-k gate dielectric are possible. Moreover, NiSi 2 is the most Si-rich phase among nickel silicides family and thermally stable. Self-organized (111) faceted NiSi 2 source/drain structure is thus quite promising for future CMOS devices

Self-organized (111) faceted NiSi2 source and drain structure with segregated dopants in the NiSi2/Si interfaces has been proposed for aggressively scaled SOI MOSFETs. The advantages of this source and drain structure are a superior short-channel effect (SCE) immunity and a very small parasitic resistance. The SCE is suppressed by a trapezoidal shape of the channel and by a small variation in the channel length that is obtained thanks to the epitaxial growth of NiSi2 on Si. The significant effects of the channel shape and the variation-free channel length are also confirmed by the numerical simulation. Owing to the low-temperature annealing at 600degC for NiSi2 formation and dopants activation, wider selections of gate metal and high-k gate dielectric are possible. Moreover, NiSi2 is the most Si-rich phase among nickel silicides family and thermally stable. Self-organized (111) faceted NiSi 2 source/drain structure is thus quite promising for future CMOS devices

Fully silicided platinum gates have been proposed as metal gate electrodes for scaled complementary metal oxide semiconductor field-effect transistors (CMOSFETs). The Pt monosilicide (PtSi) phase was formed on gate dielectrics by a full silicidation reaction at 400°C. PtSi gate electrodes on SiO2 possess a high effective work function of 4.9 eV, which could be used as a possible metal gate electrode for p-MOSFETs, while at the PtSi/HfO2 interface, Fermi-level pinning is observed independent of the PtSi fabrication process. The Fermi-level pinning at the PtSi/HfO2 interface is comparable to that at the poly-Si/HfO2 interface, and Fermi-level pinning does not occur at the Pt/HfO2 interface. These results show that Fermi-level pinning is induced by the presence of silicon atoms at the HfO2 upper interface.

Threshold voltage (V/sub th/) tuning by controlling Fermi-level pinning (FLP) position on HfAlO/sub x/(N) high-k dielectrics is demonstrated for CMOSFETs. Two kinds of methods for the effective work function tuning have been proposed. One is to control the Al concentration ([Al]) in the top interface of HfAlO/sub x/(N) to modulate the FLP position. The other is the doping into the PtSi/sub x<1.0/ (partial silicide: PASI) gates on HfAlO/sub x/(N) dielectrics. Symmetrical V/sub th/ values are obtained for the cases of poly-Si gate and FUSI (foil silicide)-NiSi gate n- and p-MOSFETs when the Al concentration is controlled in HfAlO/sub x/(N).

The impact of epitaxial NiSi2 S/D on MOSFET performance has been investigated. Atomically flat NiSi2/Si (111)-facet interface and straight S/D edges irrespective of the gate edge roughness contribute to suppressing SCE

Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness

We investigate an origin of the Fermi-level pinning at the gate electrode/HfO/sub x/(N) interface, and propose a new technology for tuning the work function with a partial silicidation of Pt on HfO/sub x/ (N). It is clearly shown that the effective work functions (/spl Phi/ /sub m,eff/) of fully silicided (FUSI) NiSi and PtSi on HfO/sub x/(N) are rigidly fixed due to the Fermi-level pinning, and that the impurity doping does not help changing /spl Phi/ /sub m,eff/ at all. The large flatband voltage (VFB) shifts of FUSI PtSi MOSFETs have been observed irrespective of Si deposition processes. On the basis of these new findings, nMOSFET with pinned n+poly-Si and pMOSFET with partially pinned PtSi on HfO/sub x/ (N) for a balanced CMOS have been proposed, and both of them have shown good electrical properties. Furthermore, it is experimentally discussed that the control of the Si atom content at the PtSi/sub x//HfO/sub 2/ interface is a key factor to relax the pinning effect. The partial silicidation technology will be a most feasible method for advanced metal gate CMOS.