2018 International Conference on Solid State Devices and Materials,Novel Integration Scheme of Replacement Metal Gate Module using Pre-Metal Dielectrics with High Gap-Fill Capability and Chemical Reaction Based H2O2 Cure

Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.

Vt Tuning in High-k nMOSFETs over Metal Gate WF Control M. Kadoshima, S. Sakashita, T. Kawahara, M. Inoue, M. Mizutani, Y. Nishida, A. Shimizu, Y. Takeshima. S. Yamanari, M. Anma, R. Mitsuhashi, Y. Satoh, S. Matsuyama, A. Tsudumitani, Y. Okuno, H. Umeda, J. Yugami, H. Yoshimura, and H. Miyatake Renesas Technology Corporation, 4-1, Mizuhara, Itami, Hyogo 664-0005, Japan Panasonic Corporation, 19 Nishikujo-kasugacho, Minami-ku, Kyoto 601-8414, Japan Phone: +81-72-787-2472, Fax: +81-72-789-3023, E-mail: kadoshima.masaru@renesas.com

Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.

Effective work function (@f"m","e"f"f) values of Hf"x Ru"1"-"x alloy gate electrodes on SiO"2 metal-oxide-semiconductor (MOS) capacitors were carefully examined to assess whether the @f"m","e"f"f was determined by the crystalline structure or the composition of the Hf"xRu"1"-"x alloy. X-ray diffraction results indicated that the crystalline structures of Hf"xRu"1"-"x alloy were divided into hexagonal-Ru, cubic-HfRu or hexagonal-Hf with the increase of Hf content. The @f"m","e"f"f values could be controlled continuously from 4.6 to 4.0eV by changing the Hf content. The experimental @f"m","e"f"f value showed a good agreement with theoretical results considering the compositional ratio of pure Hf and Ru. These results suggest that the @f"m","e"f"f of Hf"xRu"1"-"x alloy gates on SiO"2 MOS capacitors is dominantly determined by the Hf"xRu"1"-"x composition rather than the crystalline structure.

We clarified the impact of the fifth material incorporation into HfSiON technology for Vth control on the reliability of high-k/metal gate stacks CMOSFETs. HfMgSiON is remarkably effective for suppressing electron traps, giving rise to a dramatic PBTI lifetime improvement for nMOSFETs. With pMOSFETs, Al incorporation is effective for the thermal deactivation of hole traps, resulting in NBTI lifetime improvement. We have established the guidelines of material selection to be incorporated into HfSiON for reliability improvement for nMOS and pMOS individually.

A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-R s (sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (~10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.

We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flatband voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n- and p-FET but they are automatically converted into dual high-k after the annealing process.

We have studied Fermi level pinning of Hf-based high-k gate stacks based on thermodynamics by our O vacancy model. Our study shows that FLP cannot be avoided when the system is under thermal equilibrium. O injection to aim O vacancy elimination is hopeless, since O vacancy elimination condition is equivalent to the Si substrate oxidation which leads to the increase in EOT. We also studied the mechanism of FLP induced by H2 anneal. FLP by H2 anneal is governed by the O vacancy annihilation reaction by reducing SiO2 interface layer. Moreover, we briefly discuss the recipe for obtaining band-edge-work-function metals.

We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAIN gate HfAlSiON p-FET for hp 32 nm low standby power (LSTP) CMOS devices. Low V, of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AIN-cap formation of TiAIN and subsequent intermixing between AIN-cap and HfSiON by high temperature annealing. There was no degradation in gate leakage current and electron mobility in TaSiN gate HfSiON n-FET even if TaSiN was formed after TiAIN removal. Thus, this technique is practical for realizing dual-metal-gate dual-high-k CMOS devices.

We have experimentally found two different mechanisms characterizing effective work function (Phim,eff) of a gate electrode on Hf-based high-k dielectrics. Interface dipoles induce both positive and negative Phim,eff shifts. The positive shift is almost independent of gate electrode materials, while the negative one is sensitive to Si composition of the gate electrode. Surface densities of the dipoles are estimated to be the order of 1014 cm-2. By making the most of two types of interface dipoles, we can expand a tunability of Phim,eff of gate electrodes on high-k (Phim,high-k)

We studied the work function of fully silicided (FUSI) PtSi formed on ultrathin HfO2 as a function of chemical composition by using X-ray photoelectron spectroscopy (XPS). In evaluating the work function, the threshold energy for photoelectrons near the lower limit in the kinetic energy scale was determined by fitting a fowler function to the measured spectra, and cross-checked by total photoelectron yield measurements. In sample preparation, after chemical vapor deposition of 100nm-thick undoped amorphous-Si on 2nm-thick HfO2/ ri-Si(100), a 100nm-thick Pt layer was formed on the a-Si layer by sputtering and followed by silicidation at 400 degrees C. In the Pt-rich near-surface region in which the Pt content is in the range of 65-73 at.%, the work function was determined to be 5.0eV within an accuracy of 100meV. With progressive low energy Ar+ ion sputtering, the work function is gradually decreased and constant at similar to 4.8eV in the region with stoichiometric composition (50%). Notice that in the region near the interface, a photoemission component with a threshold energy as low as similar to 4.65eV becomes observable in a manner that overlaps with the photoemission from PtSi, which is attributable to the photoemission from the conduction band of the n-Si (100) substrate.

Effective work function (φm,eff) values of Ru gate electrode on SiO2 and HfO2 MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φm,eff. Annealing at 400°C in the reduction (3%H2) and the oxidation (1%O2) ambient resulted in similar changes in the φm,eff of Ru/HfO2/SiO2 and Ru/SiO2 MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φm,eff value to that of RuO2 gate MOS capacitors. The oxygen concentration in the Ru/HfO2 interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φm,eff value, regardless of SiO2 or HfO2 dielectrics. This indicates that φm,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO2.

Impact of area scaling (especially narrow channel) on Vt lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that Vt becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of Vt on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge is focused on to explain this phenomenon. It is presented that excellent narrow channel characteristic can be obtained using proper La-amount range and improved annealing process.

Fully silicided platinum gates have been proposed as metal gate electrodes for scaled complementary metal oxide semiconductor field-effect transistors (CMOSFETs). The Pt monosilicide (PtSi) phase was formed on gate dielectrics by a full silicidation reaction at 400°C. PtSi gate electrodes on SiO2 possess a high effective work function of 4.9 eV, which could be used as a possible metal gate electrode for p-MOSFETs, while at the PtSi/HfO2 interface, Fermi-level pinning is observed independent of the PtSi fabrication process. The Fermi-level pinning at the PtSi/HfO2 interface is comparable to that at the poly-Si/HfO2 interface, and Fermi-level pinning does not occur at the Pt/HfO2 interface. These results show that Fermi-level pinning is induced by the presence of silicon atoms at the HfO2 upper interface.

Threshold voltage (V/sub th/) tuning by controlling Fermi-level pinning (FLP) position on HfAlO/sub x/(N) high-k dielectrics is demonstrated for CMOSFETs. Two kinds of methods for the effective work function tuning have been proposed. One is to control the Al concentration ([Al]) in the top interface of HfAlO/sub x/(N) to modulate the FLP position. The other is the doping into the PtSi/sub x<1.0/ (partial silicide: PASI) gates on HfAlO/sub x/(N) dielectrics. Symmetrical V/sub th/ values are obtained for the cases of poly-Si gate and FUSI (foil silicide)-NiSi gate n- and p-MOSFETs when the Al concentration is controlled in HfAlO/sub x/(N).

The impact of epitaxial NiSi2 S/D on MOSFET performance has been investigated. Atomically flat NiSi2/Si (111)-facet interface and straight S/D edges irrespective of the gate edge roughness contribute to suppressing SCE