In this study, we present experimental findings regarding the variability observed in transistors employing a buried channel. In weak inversion regime this arsenic implantation plays the role to adjust the threshold voltage. A set of 1D simulations is used to show the impact on current-voltage characteristics. A correlation between the leakage current and the spatial position on a 300mm wafer has been considered, as well as a Principal Component Analysis. The objective is to understand the factors contributing to this variability.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{ON}}\times C_{\text{OFF}}$</tex> of 78 fs with a breakdown voltage of 3.7 V.

An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

This work addresses the reliability of different architectures of novel high-density multi-gate transistors manu-factured in a 40 nm embedded non-volatile memory process technology. The multi-gate architectures are based on lateral transistors integrated in deep trenches built alongside the main planar transistor. These architectures increase the conduction channel width with a weak impact on the footprint. A reliability study based on AC stress tests is carried out to monitor the multi-gate oxide degradation and in particular the interaction between planar and vertical oxides is highlighted. Finally, a benchmark of stress immunity, among the three studied multi-gate architectures, is presented.

Flexibility on the gate-to-drain/source overlap length is useful for selecting the best compromise between device performance (including short channel effects and gate scaling, ON-state current, parasitic overlap capacitance), and the device reliability to hot-carrier degradation. In this paper, the performance and reliability of transistors with variable overlap is studied in a 40 nm CMOS technology. A double-hump is observed in the substrate current characteristic in function of the gate voltage for low-overlap transistors. An analysis of the origin of the second substrate current hump is conducted, and it is attributed to impact ionization at the drain-side, source-side or both depending on the overlap. TCAD simulations are performed to explain the two possible origins of the double-hump characteristic, which are degradation of the gate control over the channel due to low overlap or hot-carrier trapping. Finally, electrical characterizations are conducted to measure the degradation rate for various overlap lengths. It is observed that a longer overlap gives the transistor a longer lifetime under hot-carrier stress conditions.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

This paper addresses the reliability on a novel trench-based Triple Gate Transistor (TGT) fabricated in a 40 nm embedded Non-Volatile Memory (e-NVM) technology. In the studied device, two vertical transistors are integrated in deep trenches alongside the main planar transistor to build a TGT. The reliability of this device is investigated targeting the gate oxide degradation, that represents one of the major reliability issues in e-NVM environment. Gate stress tests are motivated by the possibility to use independently trench transistors and the main planar transistor. Thus, the reliability of each gate oxide needs to be studied separately to the others. Moreover, different DC and AC stress tests are performed and analysed to understand the degradation mechanisms effecting the TGT device.

A new transistor architecture is developed by reusing already existing fabrication process bricks in an embedded non-volatile memory (eNVM) sub-40 nm CMOS technology, resulting in a middle-voltage zero-cost transistor, ideal for low-cost products. TCAD simulations are undertaken to confirm the feasibility of the process optimization and predict the transistor performance and reliability. The new transistor is fabricated then electrically characterized. The new device shows good analogue performances for no cost added. A hot-carrier injection (HCI) degradation evaluation is performed and confirms the reliability of the device.

This letter addresses the design, implementation, and characterization of a novel high-density Triple Gate Transistor in a 40 nm embedded Non-Volatile Memory technology. Deep trenches are used to integrate two vertical transistors connected in parallel with the main planar transistor. Thanks to the built-in trenches, the proposed manufacturing process increases the transistor width without impacting its footprint. The voltage/current characteristics of a planar MOS structure are compared with the features of the new Triple Gate Transistor. The new architecture provides an improved driving capability, with an on-state drain current twice as high as its equivalent standard MOS, combined with a lower threshold voltage, suitable for low-voltage applications. Finally, the gate oxide and junction reliability are validated over the operating voltage range.

This paper presents a novel high voltage vertical trench MOS transistor designed to be used in a Non-Volatile Memory (NVM) technology. Huge hump effect is demonstrated explaining some phenomenon observed during the AC stress. Quasi-static measurements are also reported showing that this vertical trench MOS transistor can be suitable for the use in an NVM environment. Finally, the AC stress reliability results demonstrate significant instabilities of both parasitic and main transistors. The comprehension is supported by TCAD simulations.

This paper presents a junction reliability study on a new architecture of high voltage transistor with a double poly gate for Non-Volatile Memory (NVM) Technology. The experiments results are supported by TCAD simulations. The drain-bulk AC stress was performed on the new architecture and compared with the conventional demonstrating an important improvement in terms of reliability, for different bias conditions, taking advantage of its design architecture. Finally, process and design optimizations of the new architecture are presented.

The eStM (embedded Select in Trench Memory) is a floating gate based non-volatile memory cell conceived, developed and industrialized by STMicroelectronics for General Purpose and Secure Microcontrollers embedded applications. Thanks to its unique architecture, the eStM cell gathers the advantages of a conventional split-gate NVM cell together with a more compact cellbit area than a typical 1T Flash Memory cell, and it is claimed to represent the scalability limit for a floating gate based NOR NVM.

This paper discusses an innovative architecture of charge storage NVM cell, which outpaces state-of-the-art in term of bit-cell area. This new concept of memory cell is used today in production for microcontrollers. After cell architecture and activation description, we will present process flow integration challenges, process optimizations and single cell characterizations.

Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40 nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs test chips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is, first, based on analog bitmap acquisition on 512kB test chip, followed by correction of spatial variabilities like peripheral circuits' influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally, such an analysis tool enhances the advantageous properties of a test chip, its large memory cell statistics and its product-like organization, to give more reliable data. It yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level.

Ce papier décrit le développement des prochaines générations de mémoires non volatiles (NVM). Ce travail se focalise dans un premier temps sur un rappel des technologies mémoires embarquées dites classiques, intervenant sur de nombreuses applications à base de microcontrôleurs. L’accroissement de ce champ d’applications engendre le respect de nombreux critères (ultra basse consommation, augmentation de puissance, etc.) nécessitant une évolution technologique vers des noeuds avancés comme le 40nm et le 28nm. Un état de l’art des architectures actuelles permettra alors de découvrir les différentes technologies existantes et de comprendre les procédés utilisés. Nous aborderons d’abord les notions théoriques utilisées, puis les freins potentiels à anticiper dans cette génération de mémoire et ses possibles améliorations.

This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transistors used in analog and digital applications is 5% higher due to the reduction in the STI-induced, compressive stress in the channel. The polysilicon wall could be added automatically in digital standard cells during cad to mask operation without increasing the size of the cells. Finally, the speed frequency of CMOS inverter ring oscillators designed with low-voltage MOSFETs used in digital standard cells is increased by 6% when a polysilicon wall is added around NMOS transistors. Moreover, the static current of ring oscillators remains unchanged.