08:30 5.5.1 MNSIM: SIMULATION PLATFORM FOR MEMRISTOR-BASED NEUROMORPHIC COMPUTING SYSTEM Speaker: Lixue Xia, Tsinghua University, CN Authors: Lixue Xia1, Boxun Li1, Tianqi Tang1, Peng Gu2, Xiling Yin1, Wenqin Huangfu1, Pai-Yu Chen3, Shimeng Yu3, Yu Cao3, Yu Wang1, Yuan Xie2 and Huazhong Yang1 1Tsinghua University, CN; 2UC Santa Barbara, US; 3Arizona State University, US Abstract Memristor-based neuromorphic computing system provides a promising solution to significantly boost the power efficiency of computing system. Memristor-based neuromorphic computing system has a wide range of design choices, such as the various memristor crossbar cell designs and different parallelism degrees of peripheral circuits. However,a memristor-based neuromorphic computing system simulator, which is able to model the system and realize an early-stage design space exploration, is still missing. In this paper, we develop a memristorbased neuromorphic system simulation platform (MNSIM). MNSIM proposes a general hierarchical structure for memristorbased neuromophic computing system, and provides flexible interface for users to customize the design. MNSIM also provides a detailed reference design for large-scale applications. MNSIM embeds estimation models of area, power, and latency to simulate the performance of system. To estimate the computing accuracy of memristor crossbar, MNSIM proposes a behavior-level model between computing error rate and crossbar design parameters considering the influence of interconnect lines and nonideal device factors. The error rate between our accuracy model and SPICE simulation result is less than 1%. Experimental results show that MNSIM achieves more than 7000 times speed-up compared with SPICE and obtains reasonable accuracy (more than 90%). MNSIM can further estimate the trade-off between computing accuracy, energy, latency, and area among different designs for optimization. Download Paper (PDF; Only available from the DATE venue WiFi)

Editor's note: In this article, the authors present a circuit-level macro model (“NeuroSim” simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. The model is used to analyze the impact of analog synapse device characteristics on the performance of a two-layer multi-layer perceptron (MLP) neural network and identify critical device properties (on/off ratio and asymmetry, in this case) to guide technology development.-An Chen, Semiconductor Research Corporation.

Energy efficient hardware implementation of artificial neural network is challenging due the 'memory-wall' bottleneck. Neuromorphic computing promises to address this challenge by eliminating data movement to and from off-chip memory devices. Emerging non-volatile memory (NVM) devices that exhibit gradual changes in resistivity are a key enabler of in-memory computing-a type of neuromorphic computing. In this paper, we present a review of some of the NVM devices (RRAM, CBRAM, PCM) commonly used in neuromorphic application. The review focuses on the trade-off between device parameters such as retention, endurance, device-to-device variation, speed and resistance levels, and the interplay with target applications. This work aims at providing guidance for finding the optimized resistive memory devices material stack suitable for neuromorphic application.

Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies. NeuroSim provides flexible interface and a wide variety of design options at the circuit and device level. Therefore, NeuroSim can be used by neural networks (NNs) as a supporting tool to provide circuit-level performance evaluation. With NeuroSim, an integrated framework can be built with hierarchical organization from the device level (synaptic device properties) to the circuit level (array architectures) and then to the algorithm level (NN topology), enabling instruction-accurate evaluation on the learning accuracy as well as the circuit-level performance metrics at the run-time of online learning. Using multilayer perceptron as a case-study algorithm, we investigated the impact of the "analog" emerging nonvolatile memory (eNVM)'s "nonideal" device properties and benchmarked the tradeoffs between SRAM, digital, and analog eNVM-based architectures for online learning and offline classification.

Binary Neural Networks (BNNs) have been recently proposed to improve the area-/energy-efficiency of the machine/deep learning hardware accelerators, which opens an opportunity to use the technologically more mature binary RRAM devices to effectively implement the binary synaptic weights. In addition, the binary neuron activation enables using the sense amplifier instead of the analog-to-digital converter to allow bitwise communication between layers of the neural networks. However, the sense amplifier has intrinsic offset that affects the threshold of binary neuron, thus it may degrade the classification accuracy. In this work, we analyze a fully parallel RRAM synaptic array architecture that implements the fully connected layers in a convolutional neural network with (+1, −1) weights and (+1, 0) neurons. The simulation results with TSMC 65 nm PDK show that the offset of current mode sense amplifier introduces a slight accuracy loss from ∼98.5% to ∼97.6% for MNIST dataset. Nevertheless, the proposed fully parallel BNN architecture (P-BNN) can achieve 137.35 TOPS/W energy efficiency for the inference, improved by ∼20X compared to the sequential BNN architecture (S-BNN) with row-by-row read-out scheme. Moreover, the proposed P-BNN architecture can save the chip area by ∼16% as it eliminates the area overhead of MAC peripheral units in the S-BNN architecture.

This paper presents a design of strong physical unclonable function (PUF) exploiting the sneak paths in the resistive X-point array. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs. To eliminate the undesired collision or diffuseness in X-point PUF with "analog" resistance distribution and "digital" resistance distribution is employed in this paper. The effect of design parameters and non-ideal properties in X-point array on the performance of X-point PUF is systematically investigated by Simulation Program with Integrated Circuit Emphasis (SPICE) simulation. The simulation results show that-1) the PUF's performance presents strong dependence on the percent of cells in the on-state, thus should he carefully optimized for the robustness against the reference current variation of the sense amplifier; 2) the interconnect resistance decreases the column current thus the reference current should scale down with the scaling of technology node; 3) larger on/off ratio is desired to achieve low power consumption and high robustness against reference current variation; and 4) the device-to-device variation might degrade the performance of X-point PUF, which can be mitigated with write-verify programming scheme in the PUF construction phase. In addition, the proposed X-point PUF presents no correlation between challenges and responses, and strong security against the possible SPICE modeling attack and machine learning attack. Compared with the conventional Arbiter PUF, the X-point PUF has benefits in smaller area, lower energy, and enhanced security.

For deep-neural-network (DNN) processors [1-4], the product-sum (PS) operation predominates the computational workload for both convolution (CNVL) and fully-connect (FCNL) neural-network (NN) layers. This hinders the adoption of DNN processors to on the edge artificial-intelligence (AI) devices, which require low-power, low-cost and fast inference. Binary DNNs [5-6] are used to reduce computation and hardware costs for AI edge devices; however, a memory bottleneck still remains. In Fig. 31.5.1 conventional PE arrays exploit parallelized computation, but suffer from inefficient single-row SRAM access to weights and intermediate data. Computing-in-memory (CIM) improves efficiency by enabling parallel computing, reducing memory accesses, and suppressing intermediate data. Nonetheless, three critical challenges remain (Fig. 31.5.2), particularly for FCNL. We overcome these problems by co-optimizing the circuits and the system. Recently, researches have been focusing on XNOR based binary-DNN structures [6]. Although they achieve a slightly higher accuracy, than other binary structures, they require a significant hardware cost (i.e. 8T-12T SRAM) to implement a CIM system. To further reduce the hardware cost, by using 6T SRAM to implement a CIM system, we employ binary DNN with 0/1-neuron and ±1-weight that was proposed in [7]. We implemented a 65nm 4Kb algorithm-dependent CIM-SRAM unit-macro and in-house binary DNN structure (focusing on FCNL with a simplified PE array), for cost-aware DNN AI edge processors. This resulted in the first binary-based CIM-SRAM macro with the fastest (2.3ns) PS operation, and the highest energy-efficiency (55.8TOPS/W) among reported CIM macros [3-4].

Emerging non-volatile memory (eNVM) based synaptic devices are attractive for the replacement of SRAM in the hardware implementation of artificial neural networks (ANNs). However, one of the critical challenges for eNVM is the reliability concerns due to data retention and write endurance failures. This paper investigates the impact of these two failures in the multilayer perceptron (MLP) using our developed NeuroSim+ simulator. For the retention failure in offline classification, we consider various possible conductance drift scenarios and the reported physical model based on conductance variation. The results confirm that faster degradation on the classification accuracy is highly correlated with larger deviation in the weighted sum. For the endurance failure in online learning, the strength of conductance tuning is assumed to become weaker over write pulse cycles. The analysis suggests that the learning accuracy is less impacted because the network is able to adapt itself and activate more synapses to participate in the weight update when the tuning capability of synapses are degraded.

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on-formation of filaments in an amorphous medium-is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

Dense analog synaptic crossbar arrays are a promising candidate for neuromorphic hardware accelerators due to the ability to mitigate data movement by performing in-situ vector-matrix products and weight updates within the storage array itself. However, many analog weight storage cells suffer from long latencies or low dynamic ranges, limiting the achievable performance. In this work, we demonstrate that the voltage-controlled partial polarization switching dynamics in ferroelectric-field-effect transistors (FeFET) can be harnessed to enable a 32 state non-volatile analog synaptic weight cell with large dynamic range (67 x) and low latency weight updates (50 ns) for an amplitude modulated pulse scheme.

An array of multi-level resistive memory devices (RRAMs) can speed up the computation of deep learning algorithms. However, when a pre-trained model is programmed to a real RRAM array for inference, its accuracy degrades due to many non-idealities, such as variations, quantization error, and stuck-at faults. A conventional solution involves multiple read-verify-write (R-V-W) for each RRAM cell, costing a long time because of the slow Write speed and cell-by-cell compensation. In this work, we propose a fundamentally new approach to overcome this issue: random sparse adaptation (RSA) after the model is transferred to the RRAM array. By randomly selecting a small portion of model parameters and mapping them to on-chip memory for further training, we demonstrate an efficient and fast method to recover the accuracy: in CNNs for MNIST and CIFAR-10, ~5% of model parameters is sufficient for RSA even under excessive RRAM variations. As the back-propagation in training is only applied to RSA cells and there is no need of any Write operation on RRAM, the proposed RSA achieves 10-100X acceleration compared to R-V-W. Therefore, this hybrid solution with a large, inaccurate RRAM array and a small, accurate on-chip memory array promises both area efficiency and inference accuracy.

Synaptic devices based on emerging non-volatile memory devices have been proposed to emulate analog synapses for neuro-inspired computing. However, the non-ideal device characteristics such as nonlinear and asymmetric weight increase/decrease, and finite on/off ratio, may adversely affect the learning accuracy at the system-level. In this paper, we present a device-circuit-algorithm co-simulation framework, i.e. NeuroSim, to systematically the metrics such as accuracy, area, latency and energy for online learning with synaptic devices. We surveyed a few representative synaptic devices in literature, and concluded that today's realistic devices are difficult to achieve accurate and fast learning. Finally, the targeted and ideal specifications for synaptic device engineering are proposed.

The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar / pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (Pr) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark on-chip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.

In a neuromorphic computing system, the complex CMOS neuron circuits have been the bottleneck for efficient implementation of weighted sum operation. The phenomenon of metal-insulator-transition (MIT) in strongly correlated oxides, such as NbO2, has shown the oscillation behavior in recent experiments. In this work, we propose using a MIT device to function as a compact oscillation neuron, achieving the same functionality as the CMOS neuron but occupying a much smaller area. Pt/NbOx/Pt devices are fabricated, exhibiting the threshold switching I-V hysteresis. When the NbOx device is connected with an external resistor (i.e., the synapse), the neuron membrane voltage starts a self-oscillation. We experimentally demonstrate that the oscillation frequency is proportional to the conductance of the synapse, showing its feasibility for integrating the weighted sum current. The switching speed measurement indicates that the oscillation frequency could achieve >33 MHz if parasitic capacitance can be eliminated.