Over the years, different interpretations of Rent's rule and different ways of estimating the Rent parameters have emerged. In general, these parameters are extracted from the average terminal-gate relationship for a set of circuit modules. We show that this relationship (the Rent characteristic) strongly depends on the definition of the circuit modules. These can be generated in many different ways, either from the topology of the circuit graph or, in a geometric way, by cutting regions from a circuit layout. The resulting Rent parameters can be quite far apart. This paper discusses the fundamental differences between the topological and the two geometric interpretations of the Rent characteristic that are expected to be most appropriate for current wirelength estimation techniques. Our discussion is based on experimental data, as well as on a theoretical model that can be used to estimate certain geometric Rent characteristics from the topological Rent parameters. Using this model, we derive a theoretical lower limit to the value of the average geometric Rent exponent. We also study the impact of the placement approach and placement quality on the geometric Rent characteristics.

This paper presents an FPGA hardware implementation of a bar code decoder using the EAN-13 standard. The design was implemented on an FPGA situated on an ATMEL FPLSIC (field programmable system level integrated circuit, AT94K40-25DQC). The design has comparable performance and is in many ways more robust than commercially available devices. However, to the authors' knowledge, these all use a microprocessor while our design is purely dedicated hardware.

Though it has become one of the most popular techniques for a priori wirelength estimation, Donath's method is heavily constrained by the underlying circuit and architecture models. In this paper, we propose analytical and numerical extensions to this model to overcome some of these constraints. It turns out that, with our extensions, Donath's model correlates very well with experimental data. This makes it particularly well suited for, among others, the parametric exploration of placement options.

For the development and evaluation of new algorithms, architectures and technologies, a huge amount of benchmark circuits with suitable characteristic parameters are required. Synthetic circuits are a viable alternative to real circuits for compiling benchmark suites. A major advantage of synthetic benchmark circuits is that full control of the important parameters is provided. In this paper, an existing netlist generation algorithm based on bottom-up clustering of subcircuits according to Rent’s rule is extended to generate circuits that are more realistic than before. The stochastic properties of the Rent behavior are taken into account, and improvements have been made to increase the accuracy of the imposed Rent characteristics. This guarantees a realistic structure of the interconnection topology, which can be adjusted in a controlled manner. A scheme for combinational loop prevention has been augmented with a delay control mechanism, such that they are truly suitable for timing-driven applications. An indirect validation approach is used to verify that existing placement algorithms exhibit comparable behavior for both real and synthetic

The complexity of the interconnect topology of a circuit is well captured by Rent's rule. This rule can be applied for a priori wire-length estimation, which is useful for improving the quality of generated layouts, and could be used for reducing the number of design iterations. It can also successfully be applied for the generation of synthetic benchmark circuits. However Rent's role is an empirical approximation, and there are many deviations. This paper describes possible extensions to Rent's rule and discusses some of its applications

A priori wirelength estimates are based on a terminal-gate relationship known as Rent's rule. Conventional models apply Rent's rule in 2D on square or diamond-shaped regions. However, more advanced applications of wirelength estimation require the use of Rent's rule on layout regions with different shapes. In this paper, we systematically study the layout Rent parameters of rectangular regions in a 2D layout medium. For this purpose, we derive a theoretical model for the pin versus gate relationship for layout regions of any given shape. Using this model to find an estimation of the layout Rent parameters of rectangular regions with a given aspect ratio, we show that there is a significant dependency of the Rent coefficient on that aspect ratio. We experimentally verify these results with synthetic, as well as industrial benchmark circuits. Furthermore, our model relates the layout Rent parameters of a circuit to its intrinsic partitioning properties. This leads to a fundamental limit on the value of the layout Rent exponent for circuits, embedded in a 2D layout medium.

Rent's rule can be derived by direct partitioning of the circuit netlist, by indirect partitioning of the placed layout, or by averaging the number of terminals for various equally large regions of the placed circuit. It is shown that all three methods may produce different results. After investigation of the fundamental reasons for these differences, three distinct effects can be identified. The boundary and the embedding effect is present with all placement approaches, though the embedding effect may be (partly) nullified by the grid effect that may occur with some partitioning-based placement algorithms. One of the main applications of Rent's rule is the estimation of wire length distribution. Both flat and hierarchical placement models can be applied, though experiments show that for the current state-of-the-art estimation techniques the latter produces better results, even for layouts that were generated using a flat placement approach. Which Rent parameters and occupation probability function should be used depends on the placement algorithm. We discuss various possibilities and present a new occupation probability function that allows better wire length estimations of partitioning-based placements.

Rent's rule has been successfully applied to a priori estimation of wire length distributions. However, this approach is very restrictive: the circuits are assumed to be homogeneous. In this paper, recursive clustering is described as a more advanced model for the partitioning behavior of digital circuits. It is applied to predict the variance of the terminal count distribution. First, the impact of the block degree distribution is analyzed with a simple model. A more refined model incorporates the effect of stochastic self similarity. Finally, the model is further extended to describe the effects of heterogeneity. This model is a promising candidate for more accurate a priori estimation tools.

In the past, Rent's rule has been successfully applied for a priori estimation of wire length distributions. Devia- tions to Rent's rule appear due to the existence of hetero- geneity. This can be classied in hierarchical and spa- tial heterogeneity. Stochastic models for the intercon- nection complexity, based on Rent's rule, are introduced. A coarse model shows that the variance follows a power law relationship. A more rened model incorporates the eect of local spatial heterogeneity. Experiments show that this is sucient to model the variance of the ter- minal count distribution. Finally, the model is further extended to incorporate global spatial heterogeneity.

In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic approach for the generation and evaluation of synthetic benchmark circuits is presented. A number of existing benchmark generation methods are examined using direct validation of size and topological parameters. This exposes certain features and drawbacks of the different methods.

The design of a VLSI chip consists of a number of steps, and is usually subject to a number of constraints. During each step estimates of the final design properties are used to steer the design tasks. If the design does not meet the constraints, part of the design must be redone. This is very time-consuming, hence the need for good prediction methods. One of the most important aspects of a design is the interconnection complexity, which is mainly determined by the Rent characteristics and the net degree distribution. A main design task is logic synthesis, which consists of both logic optimization and technology mapping. In this paper the impact of these steps on the Rent characteristics and net degree distribution of the circuit graph is analyzed. A circuit mapped to a simple technology library results in a net degree distribution with relatively more two-terminal nets, and relatively less multi-terminal nets. Also, faster circuits have a more profound Rent region II, a higher average terminal count in region I, and sometimes even a higher Rent exponent in region I.

For the development and evaluation of computer-aided design tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included

We have developed ESCAPE, an easy-to-use, highly interactive portable PC-based simulation environment aimed at the support of computer architecture education. The environment can simulate both a microprogrammed architecture and a pipelined architecture with single pipeline. Both architectures are custom-made, with a certain amount of configurability. Other tools, such as a memory monitor, assembler/disassembler and analysis tools, such as on-the-fly generation of pipeline activity and usage diagrams, are integrated with the environment. Based upon our limited experience with the material so far, we can state that the results are excellent. Students invariantly respond very positively, and the evaluations indicate a far deeper understanding than was previously attainable by using only the traditional textbook-and-paper-problems approach.