This work investigates the thermal characteristics of gallium nitride (GaN) high-electron mobility transistors (HEMTs) for power applications. Exemplarily, a 650-V class HEMT is analyzed by different thermal characterization methods such as transient I-V measurements, infrared (IR) microscopy, and simulations, presenting a comprehensive insight into the thermal behavior. A new electrothermal model function is derived for the extraction of thermal parameters by transient I-V measurements, and it is not limited to the linear region of the output characteristic, as a model presented in previous work, but also applicable in the saturation region. Fifth-order Foster model parameters are extracted for different operating points in linear and saturation regions. For verification and better understanding, the measurements are also performed by IR microscopy at same operating points enabling the characterization of the device's surface temperature distribution. Two new analytical models allow the interpretation of the temperature distribution and are used as fit formulas for extracting the thermal parameters found by IR microscopy. Finally, the research includes an investigation using technology computer-aided design (TCAD) simulation, followed by a thermal 3-D finite element simulation. The results allow a deeper understanding of the electrothermal behavior of GaN power HEMTs at various operating points.

This work presents a method for extracting higher order thermal models of GaN power high-electron mobility transistors (HEMTs) from I-V measurements using a typical commercial power analyzer. The approach involves deriving and fitting an electrothermal model function to measure data using a nonlinear least squares solver, yielding the thermal parameters for a higher order thermal model. Measurements are conducted using a parameter analyzer and a controlled thermal chuck, with a transient drain current response signal. The method is employed to derive the thermal impedance parameters of a 5th-order thermal Foster model for a GaN power transistor. The Foster model parameters are presented in both time and frequency domains and are subsequently transformed into Cauer model parameters. The results demonstrate strong agreement with data obtained from an on-chip temperature sensor, confirming the method's validity. This new extraction method can be executed using standard laboratory equipment typically available for the electrical characterization of GaN power transistors.

In this work, the simultaneously achievable matching bandwidth and output power of AlScN-based high electron mobility transistors (HEMTs) are derived and compared to conventional AlGaN, GaAs, and Si devices. Moll’s method is used to extract time delays resulting in carrier velocities close to 1 $\times$ 10 $^{\text{7}}$ cm/s for sheet carrier densities $\ge$ 1.5 $\times$ 10 $^{\text{13}}$ cm $^{-\text{2}}$ . Subsequently, theoretical current densities of 2.5–4 A/mm and a maximum transconductance higher than 600 mS/mm are derived for low barrier thicknesses of 5–10 nm and Sc-concentrations of 5%–20%. The matching bandwidth is estimated by the Bode–Fano criterion and connected to the output power of the transistor by the power-bandwidth product, which accounts for both parameters simultaneously. AlScN-based devices are found to exhibit a 4.5-times higher power-bandwidth product compared to conventional AlGaN-based HEMTs, quantifying the enormous, theoretical limits. Experimental data already show an improvement by a factor of 1.45 for AlScN-based devices, even in this early stage of development, which proves their superior properties, when aiming for wideband high-power millimeter-wave (mm-wave) devices.

This work shows the co-integration of the lateral GaN technology with a vertical power device, the current aperture vertical electron transistor (CAVET). The experimental proof-of-concept of a large-area CAVET power device controlled by a lateral HEMT push-pull driver stage with current sensing using a sense-CAVET is demonstrated in a double-pulse measurement setup at 40 V, up to 2.4 A, and 500 kHz. The current is mirrored via a sense-CAVET with a small gate width and converted with a transimpedance amplifier. The response time of the current measurement is approx. 60 ns. In addition to the switching waveforms, static measurements of the vertical and lateral devices and switching waveforms are shown. Thus, this GaN CAVET technology demonstrates the possibility of monolithic lateral device integration compared to other vertical device approaches and may enable future vertical GaN power ICs.

In this work, the off-state characteristics of AlScN/GaN high electron mobility transistors (HEMTs) grown by metalorganic chemical vapor deposition (MOCVD) were studied and directly compared to an AlGaN- and an AlN-HEMT grown in the same MOCVD. Pinch-off instability and leaky capacitive measurements were observed for AlScN-based HEMTs, which was correlated with a higher ideality factor and lower effective potential barrier height than the AlGaN and AlN-HEMTs. However, the reverse bias characteristics exhibited a sudden drain-current increase without a significant increase in gate-leakage current. The drain-leakage current is assumed to be related to a parasitic channel across the AlScN-barrier as a result of trap-assisted carrier transport with a Poole–Frenkel characteristic. The demonstrated pinch-off instability led to significant gain expansion in load-pull measurements and early soft-breakdown, which, in turn, limits the achievable voltage-margin. The results demonstrate a key issue to reveal the full potential of AlScN-based HEMTs for mm-wave applications.

In this work, a comprehensive study on the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) regrown on Mg-implanted layers is shown. A comparably sharp doping profile into regrown AlGaN/GaN-stacks was verified by secondary-ion mass spectrometry (SIMS) even at standard metal–organic chemical vapor deposition (MOCVD) temperatures above 1000 °C. Static and dynamic characterization by a full 100-mm wafer map exhibited neither an impact on the threshold voltage, transconductance nor on the saturation current even for channel thicknesses as low as 150 nm. Slight current collapse was observed at high OFF-state conditions with large recovery times above 5 s indicating rather slow traps from the nonconnected p-GaN. Within the leakage current, three different mechanisms were identified across the vertical epi-stack. While variable-range hopping (VRH) dominates below ${V}_{{\text {DS}}}$ = 35 V, the Pool–Frenkel emission (PFE) was identified for ${V}_{{\text {DS}}} >35$ V. At high electric fields ( ${E} >$ 1 MV/cm), the devices revealed either a direct change from PFE to drain-induced barrier lowering (DIBL) or a change from PFE to space-charge-limited currents (SCLCs) to DIBL was observed. The device results demonstrate the feasibility of the demonstrated process for reproducible device fabrication on large-scale wafers with low channel thicknesses for future device developments of CAVETs, SJ-HEMTs, p-GaN back gates, and intrinsic body diodes.

In this letter, a vertical GaN power transistor driven by lateral devices fabricated in the same technology is demonstrated. The technology combines a co-integrated large area current aperture vertical electron transistor (CAVET) with high electron mobility transistors (HEMTs) for the realization of the driver on a GaN substrate. The quasi-monolithic integrated driver stage consists of two HEMT devices in a push-pull configuration. The CAVET and HEMTs are characterized, separated, packaged, and measured in a double pulse test setup with inductive load. The voltage signals of the HEMT driver with CAVET are shown in continuous operation up to 5 MHz and extreme duty-cycles. In pulsed operation, switching characteristics and waveforms under load up to 120 V and 4.1 A are shown with turn-on/-off switching times of 17.3/2.8 ns. Finally, this work demonstrates a GaN technology that combines the functional integration of a driver stage with a vertical power transistor and thus opens the pathway to continue lateral GaN power integration in vertical device concepts.

•Monolithic GaN-on-Si power converter ICs require highside device integration.•GaN-on-Si, GaN-on-SOI, and GaN-on-Si with p-n junction enable high-side isolation.•Floating Si, Si p-n junctions, and buried Si oxides form vertical capacitances.•Isolation capacitances increase (SOI, p-n) or decrease (floating) the switching loss.•High-side logic and drivers require a local substrate to switch-node termination.

The allocated frequency bands of next-generation wireless communication networks will be shifting further up in the spectrum to be able to meet the stringent data rate requirements. Doing so, demands higher bandwidth capabilities from the electronic devices in the RF chain. Numerous cutting-edge systems are using AlGaN/GaN-HEMT based components, in particular in the transmit chain, due to their favorable combination of output power and bandwidth capability. Still, this semiconductor technology is approaching an upper bound in this regard, known as the Bode-Fano limit. Devices based on an AlScN/GaN heterointerface have been identified as candidates to push these boundaries and enable components that deliver higher power over a broader frequency range. We report on the status of MOCVD-grown AlScN/GaN HEMTs, their current capabilities but also on challenges that still hamper the exploitation of the material system's full potential. The first reported AlScN/GaN HEMTs were fabricated on epitaxial stacks grown by MBE. However, the majority of commercial GaN-based HEMT technologies is relying on MOCVD-grown epitaxy due to higher growth rate and lower cost of operation. We managed to grow AlScN/GaN heterostructures showing sheet carrier densities (n S ) of up to 3·10 13 cm -2 and mobilities of 1100 cm 2 /Vs. These results were achieved with a MOCVD reactor that had been modified to cope with the low vapor pressure of the used precursors Cp 3 Sc and (MCp) 2 ScCl. Depending on the temperature, the obtained growth rates were as high as 0.015 nm/s. Currently, further precursors with allegedly higher vapor pressure are evaluated that should allow for even higher growth rates, further improving the quality of the fabricated heterostructures. Furthermore, HEMT devices were fabricated on top of the epitaxial wafers that showed power densities (P out ) of up to 8.4 W/mm and power-added efficiencies (PAE) of more than 48 % at a frequency of 30 GHz, even surpassing the current state-of-the-art in terms of combined P out and PAE of Ga-polar devices. However, there are still a number of unsolved issues visible in most reported AlScN/GaN HEMT devices, regardless of the used growth method. One is concerning the level of leakage currents and the consequential premature soft breakdown. The root cause of this phenomena is not yet fully understood but is believed to originate from poor dielectric/isolating properties of the Sc-containing barrier. This hypothesis is supported by a comparably high level of impurites that is found in the AlScN layers. Minimizing theses residuals by purification of the precursors is, therefore, necessary to further improve the electrical device characteristics. Secondly, transport properties of AlScN/GaN heterointerfaces are not as well studied as more established junctions, e.g., AlGaN/GaN and AlN/GaN. An important parameter that has not been experimentally identified for 2DEGs induced by AlScN/GaN heterojunctions yet, is the saturation drift velocity (v sat ). It is of particular importance since the Bode-Fano limit, among other, depends on it. Since the extension of the latter is one of the great promises of AlScN/GaN devices, it is clear that the value of v sat is essential to know in order to make quantitative predictions of the level of improvement that is achievable in terms of bandwidth capability but also with regard to power density. We will give an overview of recent advances of MOCVD-grown AlScN/GaN HEMTs with respect to their capability to extend on the achievable performance level of present GaN-based devices, in particular in the millimeter-wave frequency range. Further, we will benchmark the results against other competing technologies, i.e. GaAs pHEMT and Si-CMOS, to give an outlook of where optimized AlScN/GaN devices can takes us and where they cannot.

The impact of an Au‐free Ti/Al/Ti/TiN (20/100/20/80 nm) ohmic contact metallization on an Al 0.21 Ga 0.79 N/GaN heterostructure is investigated. Using the transfer length method and Hall measurements, the sheet resistance and the carrier concentration below the contact are analyzed, depending on the post‐deposition annealing temperature. It is shown that with increasing annealing temperature, the carrier density below the contact is enhanced. This is caused by the contact formation mechanism, leading to an extremely low contact end resistance to the sub‐contact region of 0.04 Ω mm. However, while the sub‐contact semiconductor resistance is low, the contact (front) resistance to the device channel is 0.74 Ω mm after annealing at 900 °C, indicating a depletion of the sub‐contact 2D electron gas because of alloy formation.

Non-linear output characteristics and the related turn-on voltages of GaN-based current aperture vertical electron transistors (CAVETs) are investigated experimentally. The resistive components are systematically analyzed in dependence of the device layout to determine the dominant resistances in the devices. Current–voltage (IV) and capacitance–voltage-characteristics (CV) are compared to a proposed planar-doped barrier diode (PDBD) model, and the influence of the bound sheet charge density and drift layer carrier concentration is discussed. The observed CV characteristics are in contrast to the PDBD model as a clearly voltage-dependent capacitance was observed and dopant-diffusion forming a p-type aperture was ruled out. Thermionic emission was verified by temperature-dependent IV characteristics indicating interface states causing a potential barrier. Transient drain current measurements revealed a single dominating trap level with an activation energy of EA = 1.086 ± 0.015 eV. This activation energy was attributed to carbon-related acceptor states present at the regrowth interface and the drift layer. Additional test structures revealed that the interface potential barrier and the space charge in the drift layer limit the initial charge transport causing a turn-on voltage in the devices. The results point out the significance of a precise control of the regrowth interface properties and the effective carrier density in the drift layer to enable efficient, high-power devices based on the CAVET technology.

GaN technology is on the advance for the use in power ICs thanks to space-saving integrated circuit components and the increasing number of integrated devices. This work experimentally investigates a number of key building blocks for GaN power integration. First, an overview of the active and passives devices of the technology is given with focus on area-efficient layouts for power transistors and limitations of on-chip capacitors and inductors with comparison to other IC technologies. Digital and analog basic circuits as part of device libraries are examined and optimized with regard to area-efficiency. The NOT gates have active areas as low as $56.7 ~\mu \text{m}^{2}$ and max. static currents of 0.12 mA with high noise margins. Further digital gates are presented. For the analog circuits, differential amplifiers and voltage reference concepts are presented and compared. Finally, GaN power integration is discussed, and integration levels are defined and described. The GaN technology is compared with other IC technologies, and future challenges and perspectives are shown. GaN power integration based on building blocks aims to exploit the full potential of the lateral GaN technology in order to compete with Si-based IC technologies in the future.

Abstract In this work, a large area current aperture vertical electron transistor (CAVET) is fabricated on bulk GaN substrates grown by metal organic chemical vapour deposition (MOCVD). The current blocking layer (CBL) is formed by low dose Mg‐implantation to allow for MOCVD regrowth under standard growth conditions, which simultaneously serves as an in‐situ annealing process. Small transistors are evaluated regarding gate‐aperture overlap (LGAP) to derive a robust layout in order to suppress source‐drain leakage. Optimized gate‐aperture dimensions are adopted and combined with a common comb structure design and the established gate‐source module of the lateral HEMT to demonstrate a large area CAVET comb structure. The multi‐finger device exhibits an on‐state resistance of RON = 2.15 Ω and a chip area of A = 2 × 2 mm². The large area CAVET reveals a maximum drain current of ID,MAX = 20.1 A at a drain‐source voltage of VDS = 45 V, corresponding to a power of P = 900 W.

The current aperture vertical electron transistor (CAVET) combines the high carrier mobility of the AlGaN/GaN heterostructure with the better electric field distribution of the vertical topology, allowing for higher power densities if compared with lateral high electron mobility transistors (HEMTs). The formation of a current blocking layer (CBL), without degenerating the aperture region and the subsequently overgrown AlGaN/GaN heterostructure is the key building block of such devices. Herein, a comparison of GaN:Mg nonplanar selective area growth (SAG) and Mg‐ion implantation is carried out primarily focusing on structural evolution, Mg distribution, and 2D electron gas (2DEG) performance. The epitaxial growth process in SAG is correlated to local growth increase and ridge development, and then optimized regarding mesa filling. AlGaN/GaN regrowth is analyzed regarding structural evolution after overgrowth and Mg distribution into the GaN channel. Considerably lower Mg‐distribution into subsequently grown layers is detected for implanted samples in agreement with the electrical performance of the overgrown AlGaN/GaN heterostructures. A GaN‐on‐Si quasivertical CAVET structure with an Mg‐implanted CBL and 250 nm channel thickness is fabricated. High surface quality and proper 2DEG performance demonstrate the potential use of GaN‐on‐Si CAVET's using Mg implantation for CBL fabrication.

In this work, multi-finger current aperture vertical electron transistors (CAVETs) are fabricated with co-integrated high electron mobility transistors (HEMTs). The devices are realized by Mg-ion implantation and metalorganic chemical vapor deposition (MOCVD) regrowth. The intrinsic CAVET design is optimized for robust device performance and applied on multi-finger devices having a total gate periphery of ${W}_{{\text {G}}} =13.5$ mm and ${W}_{{\text {G}}} =77$ mm. Mappings of the transfer characteristics revealed reliable turn-off behavior demonstrating the suitability of the intrinsic device layout. The largest CAVETs revealed a total ON-state resistance of ${R}_{ \mathrm{\scriptscriptstyle ON}} = 1.67\,\,\Omega $ and a maximum drain current of ${I}_{{\text {D},\text {MAX}}} =20.3$ A at ${V}_{\text {GS}} = {3}$ V. A pulse robustness of ${P}_{\text {PULS}} =976$ W at ${V}_{\text {DS}} =50$ V and a pulsewidth of 500 $\mu \text{s}$ is shown without thermal destruction. Additionally, HEMTs are co-integrated on-chip. This combination of HEMTs and reliable large area CAVETs enables the design of high-performance, monolithically integrated GaN power circuits (GaN power ICs) based on the CAVET technology.

In this work, the deep-level trapping behaviour of GaN-on-GaN current aperture vertical electron transistors (CAVETs) is characterised by means of current transient measurements and compared to AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on the same wafer. To the best of our knowledge, this represents the first analysis of deep-level traps in a GaN-based CAVET. In both structures, a single deep-level with an activation energy of (1.086 ± 0.015) eV (CAVET) and (0.812 ± 0.032) eV (HEMT) is found to dominate the observed transient responses.

AlScN/GaN heterostructures are worth investigating due to the remarkable high gradients in spontaneous polarization at their interfaces, which brings them into play for a wide field of potential high-power and high-frequency electronic applications. In this work, AlScN/GaN heterostructures for high electron mobility transistor (HEMT) structures were grown by metalorganic chemical vapor deposition. We have investigated the impact of growth parameters on thick AlScN layers and on thin AlScN/GaN heterostructures. Growth parameters, such as temperature, V/III ratio, pressure, and growth mode, were varied with the focus on surface morphology, crystal quality, and incorporation of impurities. High growth temperatures improve the surface quality and reduce impurities incorporation notably. In addition to that, a slight decrease in carbon concentration is obtained by adopting a pulsed supply of metalorganic precursors. V/III ratio and pressure did not influence the layer quality observably. Heterostructures with root mean square surface roughness values as low as 0.38 nm, revealing smooth growth steps, were achieved. The presence of two-dimensional electron gases with sheet carrier densities and mobilities of up to 2 × 1013 cm−2 and close to 900 cm2/(V s), respectively, resulted in channel sheet resistances as low as 337 Ω/sq, very suitable for AlScN/GaN HEMTs. Heterostructures with sheet resistances below 200 Ω/sq and sheet carrier densities of 5 × 1013 cm−2 were also achieved but showed significantly lower mobility.

GaN devices for high‐frequency and high‐power applications often need n‐doped GaN layers on top of their structures. Such layers can be either grown in an epitaxial reactor or formed by implantation or annealing of Si‐containing layers (e.g., a SiO 2 mask). These processes are typically performed at high temperatures, which generate the undesired effect of atom diffusion between the different epitaxial layers; consequently, the electrical performance of the final device will be hampered. Herein, an optimized epitaxial growth process of n‐GaN layers is developed with the focus on minimizing the atom diffusion process, while preserving a high material quality and excellent electrical characteristics, such as very low contact resistance for n‐GaN ohmic contacts or high electron mobility in GaN npin structures. A low growth temperature process combined with improved growth conditions to minimize the incorporation of impurities is successfully optimized and demonstrated on different epitaxial reactors.

Heterostructures made of GaN and epsilon-Ga2O3 epitaxial layers may be very interesting because they could exploit the high electron mobility of GaN combined with the ferroelectric character of epsilon-Ga2O3. We have explored the possibility of using epsilon-Ga2O3 templates, deposited by metalorganic chemical vapor deposition on sapphire substrates, in order to reduce the lattice mismatch of GaN with sapphire. Considering that epsilon-Ga2O3 is metastable and undergoes a first phase transition at around 700 degrees C, the GaN layers were deposited at two different temperatures (690 degrees C, 1050 degrees C). Preliminary electrical and SIMS investigations have evidenced the diffusion of oxygen from the epsilon-Ga2O3 to the GaN epitaxial layer, which results in an n-type conductivity and a sheet resistance as low as 70 Ohm/sq in a 1 mu m thick GaN layer. The rocking curve of the GaN layers grown epsilon-Ga2O3 /sapphire at standard high temperature (1050 degrees C) indicates a crystal quality worse than for GaN deposited directly on sapphire. In parallel, we studied the nucleation of epsilon-Ga2O3 on GaN templates. We evidenced that epsilon-Ga2O3 nucleates in 3D islands on the surface of GaN grown on on-axis sapphire, with coalescence taking place as the layer grows thicker. The use of off-cut sapphire substrates, instead, permits to inhibit islands formation, resulting in a smoother layer. The possibility of obtaining uniform and very thin epsilon-Ga2O3 layers on GaN layers opens interesting possibilities for the development of novel high electron mobility transistors (HEMT).