The IBM Z microprocessor, Telum II, has been redesigned for the zNext system to improve performance and system capacity over the previous z16 system [1]. The system topology consists of four Dual-Chip Modules (DCM), each composed of two central-processor (CP) chips per drawer. The system can be configured with up to four drawers and a total of 32 CP chips in a fully coherent shared memory system. The CP (Fig. 2.2.7) is a $600\text{mm}^{2}$ die containing 43B transistors and is designed in Samsung 5nm bulk technology [2]. It contains over 24 miles of wire and 165B vias spread across 18 layers of metal: 8 narrow-width layers for local interconnect, 8 medium width-high performance layers, and two ultra-thick layers for off-chip signal routing and power/clock distribution. The combination of die size increase and library improvements allowed us to keep 8 cores per CP, while adding a new Data Processing Unit (DPU) onto the chip. Each CP operates at 5.5GHz. Each core has a 128KB L1 instruction cache, and a 128KB data cache. Each CP also has 2 PCIe Gen5 ×16 interfaces, an M-BUS interface to the other CP on the DCM, and an X-BUS interface to every CP in the other 3 DCMs per drawer. There is 1 A-BUS interface to connect 6 out of the 8 CPs in each drawer to the other drawers in the system. The clock network is designed with a 1:1 resonant mesh covering most of the chip and three small asynchronous non-resonant meshes for the memory and PCIe interfaces. In addition, Telum II adds an on-chip voltage control loop for improved dynamic voltage management, which maintains performance without requiring higher voltages across all workloads [3]. Key system capacity and performance improvements came from enhancements to the core and the increased cache size. Telum II increases the number of L2 cache instances from 8 to 10 and uses Samsung's high-density SRAM cell to grow the L2 cache by 40% from 32MB on Telum to 36MB per L2 cache instance. Each processor core and the DPU have a private 36MB L2 cache along with an extra floating L2, which are fully connected by a 352GB/s ring. The on-chip shared virtual L3 cache increases from 256MB to 360MB. A fully populated drawer now contains 2.88GB of virtual L4 cache, up from 2GB on z16. In addition to the high-density SRAM cell, the cache growth was enabled by a 20% core area shrink from Telum. The core shrink was achieved through microarchitecture enhancements and technology. In addition to shrinking, the core added to the overall system performance through enhancements to branch prediction, I-cache prefetching, additional rename registers, and TLB optimization. The core physical design is constructed of 7 large fully abutted floorplanned blocks where the logic boundaries are removed, and the design is restructured. This methodology removes 2 levels of physical hierarchy leading to efficient area and metal usage in the core [4], [5].

The IBM zNext's Telum II processor [1] is a full-stack overhaul of its predecessor [2], featuring a modified 5nm Samsung bulk technology [3], new IBM-created standard cell and IP libraries, and a variety of further design-technology co-optimizations (DTCO). While die size grew from $530\text{mm}^{2}$ to $600\text{mm}^{2}$ (1.13×), each chip in the dual-chip module became denser, featuring 1.3T shapes (1.25×), 43B transistors (1.38×), and 38km of wire (1.28×) across 18 BEOL layers. As IBM's first 5nm processor, Telum II was a concurrent hierarchical design effort, with libraries, IP blocks (array / regfile / analog / phy / custom), and all gate-level entities designed simultaneously. These data volume and concurrent design pressures drove a variety of abstraction, modeling, and other EDA innovations in addition to those involving power, performance, area, and reliability targets.

The IBM Telum II microprocessor features eight cores operating at a base frequency of 5.5 GHz, ten 36-MB L2 caches achieving 3.6-ns access latency, a 360-MB virtual L3 cache, and a new on-chip data processing unit (DPU) for I/O acceleration. As the foundation of the IBM z17 system's dual-chip modules (DCMs), Telum II maintains high reliability and a power profile within 5% of the prior generation, while simultaneously increasing frequency and increasing latch count by 40%. Power, performance, area, and reliability enhancements span the design stack, including high-density SRAM cells from the Samsung 5-nm technology for increased cache size; design-technology co-optimizations (DTCOs) in the standard cell library image and sequential elements; physical design (PD), logic and architectural advancements to the core and artificial intelligence (AI) accelerator; and improved system-level capacity and encryption.

The POWER10™ processor designed for enterprise workloads contains 16 synchronous SMT8 cores (Fig. 2.4.1) coupled through a bi-directional high-bandwidth race-track [1] [2]. A SMT8 core with its associated cache is called a core chiplet, and a pair of core chiplets forms a 39.4mm2 design tile. Designed in a 7nm bulk technology, the 602mm2 chip (0.85× of POWER9™ [3]) has nearly 18B transistors, 110B vias and 20 miles of on-chip interconnect distributed across 18 layers of metal: 8 narrow-width layers for short range routes, 8 medium-width layers for high performance signals and two 2160nm ultra-thick metal (UTM) layers dedicated for power and global clock distribution. There are 10 input voltages as shown in Fig. 2.4.1: core/cache logic (Vdd), cache arrays (Vcs), nest logic (Vdn), two PHY voltages (Vio, Vpci), stand-by logic (Vsb), a high-precision reference voltage (Vref), DPLL voltage (VDPLL), analog circuitry voltage (VAVDD), and an interface voltage (V3P3). The C4 array contains 24477 total connections (1.25× of [3]) with 10867 power, 11879 ground and 1731 signal connections. A core and its associated L2 cache are power-gated together, while the L3 cache is power-gated independently.

IBM "Telum", the latest microprocessor for the next generation IBM Z system has been designed to improve performance, system capacity and security over the previous enterprise system [1].The system topology has changed from a two-design strategy featuring one central system-controller chip (SC) and four central-processor (CP) chips per drawer into a one-design strategy, featuring distributed cache management across four Dual-Chip Modules (DCM) per drawer, each consisting of two processor chips for both core function and system control. The CP die size is 530mm 2 in 7nm bulk technology [5] [6].The system contains up to 32 CPs in a four-drawer configuration (Fig 2.3.1). Each CP (shown in Fig 2.3.2 die photo) contains 22B transistors, operates at over 5GHz and is comprised of 8 cores, each with a 128KB L1 instruction cache, a 128KB L1 data cache and a 32MB L2 cache. Chip interfaces include 2 PCIe Gen4 interfaces, an M-BUS interface to the other CP on the same DCM and 6 X-BUS interfaces connecting to other CP chips on the drawer.6 out of the 8 CPs in each drawer have an A-Bus connection to the other drawers in the system.

The IBM z15 system improves upon the prior-generation z14 design within the same chip footprint and technology node, while featuring the addition of two cores, 33%/100%/43% additional L2/L3/L4 cache, as well as additional core features and on-chip accelerators. The largest 5-drawer system configuration includes 20 central processor (CP) chips, five system controller (SC) chips, and 40 TB of memory. With ~200 cores across all CP chips operating with 99.99999% uptime at 5.2 GHz, z15 achieves a 25% increase in system capacity and a 14% single thread performance improvement over the z14 system. In this article, we describe the key design factors and system/characterization refinement that enabled these results, including the novel 2-Mb embedded dynamic random access memory (eDRAM) cell, a new voltage droop monitor, a more comprehensive power reduction infrastructure to reduce power-limited yield, results on reliability-limited versus power-limited yield, and a characterization effort for exploring even higher frequencies, with our first reported 6-GHz values achieved in the lab at customer temperatures and voltages.

The latest IBM Z microprocessor in the z15 system has been redesigned to have improved performance, system capacity and security over the previous z14 system [1]. These achievements are made while maintaining the central processor (CP) and system controller (SC) chip die sizes at 696mm 2 in the GlobalFoundries 14nm high performance (14HP) SOI FinFET technology and 17 layers of copper interconnect [2], both design points of the z14 system. The system contains up to 20 CP and 5 SC chips. Each CP, shown in die photo A (Fig. 2.7.7), operates at 5.2GHz and is comprised of 12 cores, 3 PCle Gen4 interfaces, 256MB of L3 embedded DRAM (eDRAM) cache, two X-BUS interfaces connecting to one other CP chip and one SC chip, and a redundant array of independent memory (RAIM) interface. Each core on the CP chip has 8MB of L2 eDRAM cache as well as 256KB of L1 SRAM cache, both caches split evenly between data and instruction. Each SC, shown in die photo B, operates at half the frequency of the CP, or 2.6GHz, has 960MB of L4 eDRAM cache, X-BUS interfaces connecting to half of the CP chips in the drawer and four A-BUS interfaces connecting to the SC chips on the other drawers in the system. The CP contains 9.2B transistors and the SC contains 12.2B transistors. The total 10 bandwidth of the CP and SC are 2.3Tb/s and 5.6Tb/s, respectively.

The IBM Z microprocessor in the z14 system has been redesigned to improve performance, system capacity, and security [1] over the previous z13 system [2]. The system contains up to 24 central processor (CP) and 4 system controller (SC) chips. Each CP, shown in die photo A (Fig. 2.2.7), operates at 5.2GHz and is comprised of 10 cores, 2 PCIe Gen3 interfaces, an IO bus controller (GX), 128MB of L3 embedded DRAM (eDRAM) cache, X-BUS interfaces connecting to 2 other CP chips and one SC chip, and a redundant array of independent memory (RAIM) interface. Each core on the CP chip has 4MB of eDRAM L2 Data cache and 2MB of eDRAM L2 Instruction cache, with 128KB SRAM Instruction and 128KB SRAM Data L1 caches. Each SC, shown in die photo B (Fig. 2.2.7), operates at 2.6GHz and has 672MB of L4 eDRAM cache, X-BUS interfaces connecting to CP chips in the drawer and A-BUS interfaces connecting SCs on the other drawers. Both chips are 696mm 2 and are designed in Global Foundries 14nm high performance (14HP) SOI FinFET technology with 17 layers of copper interconnect [3]. The CP contains 6.1B transistors, while the SC contains 9.7B transistors. The total IO bandwidth of the CP and SC are 2.9Tb/s and 5.5Tb/s, respectively.

The IBM z14 is the latest update in the storied history of IBM mainframes. Reliability, availability, security, and scalability are the foundation of the IBM mainframe line. System reliability and availability targets are in excess of 10 years, requiring rigorous chip characterization processes. In this paper, we discuss some of the many processes used to ensure that lifetime. An additional part of this reliability is power management (PM). The 5.2-GHz high-power design of the central processor chip requires advanced on-die PM capabilities to adapt to power intensive instruction streams. We also discuss a number of improvements to the critical path monitoring design used to manage power supply voltage droops, reducing response time and the impact on system performance. Finally, we compare a set of simulations and hardware results to validate our power fluctuation models.

In designing the IBM z14 microprocessor chipset, we discarded many of our previous assumptions and processes in favor of newer, more radical approaches. These new approaches were the result of learning from previous designs as well as this design's performance and schedule requirements. In this paper, we discuss some of the more significant changes to our methodology, including a dramatic departure from our very hierarchical integration design style to a flatter, more nimble approach. We also discuss improvements to our design's power management architecture for managing power-supply noise. Finally, we discuss changes to our simulation environment, targeted at increasing both the number of simulation cycles and simulation logic coverage.

The IBM z14 design was built with the 14-nm high performance silicon-on-insulator (SOI) technology of GLOBALFOUNDRIES. This was the first technology node after IBM transitioned from its integrated fabrication facility to operating in a fabless environment, driving significant changes to design processes and methodology. In addition to this partnership, the 14-nm technology introduced significant changes relative to previous technology nodes, including the introduction of fin-shaped field-effect transistors, the use of double patterning for the lowest back-end-of-line layers, and the introduction of middle-of-line layers to exploit contact layers for local interconnects. This combination of technical and business challenges required numerous large-scale innovations for our design, design team, and design methodologies. In this paper, we provide a survey of these innovations, including the fin-based standard cell image, deeply scaled SOI self-heating/electromigration verification, routing strategies to handle double-patterning with interlayer via awareness, fill automation to enable simultaneous design of multiple layers of hierarchy, and high-performance array design with the voltage and noise limitations of the 14-nm technology node.

The following corrections should be made to the published paper [1]: [...]

Monte Carlo (MC) sampling algorithms are an extremely widely-used technique to estimate expectations of functions f(x), especially in high dimensions. Control variates are a very powerful technique to reduce the error of such estimates, but in their conventional form rely on having an accurate approximation of f, a priori. Stacked Monte Carlo (StackMC) is a recently introduced technique designed to overcome this limitation by fitting a control variate to the data samples themselves. Done naively, forming a control variate to the data would result in overfitting, typically worsening the MC algorithm's performance. StackMC uses in-sample / out-sample techniques to remove this overfitting. Crucially, it is a post-processing technique, requiring no additional samples, and can be applied to data generated by any MC estimator. Our preliminary experiments demonstrated that StackMC improved the estimates of expectations when it was used to post-process samples produces by a "simple sampling" MC estimator. Here we substantially extend this earlier work. We provide an in-depth analysis of the StackMC algorithm, which we use to construct an improved version of the original algorithm, with lower estimation error. We then perform experiments of StackMC on several additional kinds of MC estimators, demonstrating improved performance when the samples are generated via importance sampling, Latin-hypercube sampling and quasi-Monte Carlo sampling. We also show how to extend StackMC to combine multiple fitting functions, and how to apply it to discrete input spaces x.

Recent studies have analyzed the minimal thermodynamic work required for a given logical map to be implemented on any physical system. These studies have focused on maps whose output does not depend on the input, e.g., bit erasure in a digital computer. In addition, they have considered physical systems whose design varies depending on the distribution of inputs to the map. However very often we are interested in implementing a map whose output depends on its input. In addition, we often want our system to implement the same map even if the systemu0027s environment changes, so that the distribution over map inputs changes. Here I introduce a thermodynamic engine that satisfies both of these desiderata. I then calculate how much work it requires, deriving an additive correction to the generalized Landauer bound of previous studies. I also calculate the Bayes-optimal engine for any given distribution over environments. I end with a short discussion on how these results relate the free energy flux incident on an organism / robot / biosphere to the maximal amount of (noisy) computation that the organism / robot / biosphere can do per unit time.

What is the "value of information" in non-cooperative games with imperfect information? To answer this question, we propose to quantify information using concepts from Shannon's information theory. We then relate quantitative changes to the information structure of a game to changes in the expected utility of the players. Our approach is based on the Multi-Agent Influence Diagram representation of games. We develop a generalization of the concept of marginal utility in decision scenarios to apply to infinitesimal changes of the channel parameters in noncooperative games. Using that framework we derive general conditions for negative value of information, and show that generically, these conditions hold in all games unless one imposes a priori constraints on the allowed changes to information channels. In other words, in any game in which a player values some aspect of the game's specification beyond the information provided in that game, there will be an infinitesimal change to the parameter vector specifying the game that increases the information but hurts the player. Furthermore, we derive analogous results for N > 1 players, i.e., state general conditions for negative value of information simultaneously for all players. We demonstrate these results numerically on a decision problem as well as a leader-follower game and discuss their general implications.