This paper presents a novel topology for a dual output linear regulator (LDO) for integrated functions in GaN technology. The proposed topology uses an alternative topology compared to the existing designs in literature and can generate a 6 V and 12 V regulated output voltage for monolithic gate drivers in 650-V normally-off GaN power transistors. This work presents the design of the circuit, the measurements and a comparison with existing solutions presented in other published papers.

This work presents a power transistor with monolithically integrated gate driver and auxiliary circuit in the same GaN-on-Si die. It presents the design, the characterization and validation tests in a PCB similarly to a final application for this device. The target application is for USB-C chargers and power supplies for data centers. The technology is 650 V pGaN with Schottky gate. Simulation from -40 to 150 °C are performed and also fabrication process variation analysis (SS, FF) compared to typical values (TT).

To increase power density, reliability and easy use, different circuits can be integrated in the same GaN-on-Si 650V die for power management. Input compatibility circuit and UVLO (undervoltage lockout) are essential circuits needed when integrating gate driver with a power transistor in the same die. This paper presents the characterization measurements of an UVLO and two different designs for input compatibility circuits with the objective to obtain one design with good process compensation for high efficiency mass production yields.

This paper presents the main characteristics of three different gate drivers monolithically integrated and realized in 650-V GaN-on-Si p-GaN Schottky gate technology. It compares the proposed circuits with state-of-the-art solutions and explains the tradeoff between propagation delay and gate driver current consumption. One of the proposed gate drivers can switch a 650-V 100 mΩ power transistor in less than 3 ns of fall time with a static power consumption of 1.1 mA. Another proposed gate driver uses a simplified approach to obtain similar performance. A third one achieves almost similar performance while requiring only one power supply rail operating in bootstrap topology. High-voltage and high-frequency measurements are presented for both zero voltage switching (ZVS) and hard switching conditions.

This paper presents the main characteristics of four different UVLO (Undervoltage Lockout) circuits for monolithic integration in 650-V GaN-on-Si Schottky p-gate technology. The dispersion of the threshold values is measured and correlated with corner analysis and Monte Carlo simulation to analyze process variation. The objective is to achieve a design with low threshold value dispersion for mass production in an emerging GaN technology that exhibits significant variation in transistor threshold values and saturation current.

The 650V AlGaN/GaN Schottky gate technology presents a gate structure that can be damaged by ESD discharges. Therefore, discrete power GaN devices can have ESD protection circuits to be used in diverse applications. The use of diodes in series for clamping negative voltages in the gate of HEMT power transistors is discussed. The disadvantage of those solutions is the large area required by ESD diodes and the low breakdown value achieved. To increase the performance of ESD circuits while keeping the circuit consuming low area for a cost-effective solution, two circuits are presented in this paper.

This work describes two designed and fabricated circuits for power device integration in 650 V e-mode GaN-on-Si technology and gives their main measured characteristics. The first circuit is a voltage reference designed to compensate process, voltage and temperature (PVT). The advantage of this circuit over state-of-the-art circuits is its performance of regulation, low current consumption and surface required (only 100 µm x 60 µm in the first prototype built). The second circuit is a zero-crossing current detector that is also designed to be insensitive to process variations. It exhibits stable static characteristics and bandwidth observed in simulation of more than 10 MHz. The convenience of this circuit is its simplicity because no differential amplifier is used to make a comparison. Both circuits are designed to be integrated with power transistors in GaN technology to be used in ACF or other topologies capable of switching at 650 V.

This work demonstrates the impact of GaN HEMTs combined with an appropriate digital control strategy in laptop charger application. A first power stage which is based on a bridgeless PFC totem-pole architecture, is in series with a DC -DC stage, i.e., an LLC resonant converter, to achieve a full operating charger. A 300 Watt AC-DC prototype is proposed and carefully designed including a high frequency range (up to 1 MHz) for the LLC stage in order to use the advantages of GaN technology.

One way to achieve high power density in a power converter is by using a microcontroller and digitally controlled feedback loops to address some technical performance values. This paper establishes the automatic zero voltage switching (ZVS) operation in order to reduce turn-on losses on 650V GaN power transistor and maintain the temperature within acceptable range without heatsink. The algorithm presented in this paper is tested on a demo board for different values of Vdc bus voltage from 100 V up to 500 V. This paper presents the algorithm and one solution of using one analog-to-digital converter (ADC) inside the microcontroller ST32G4 to read the VDC bus voltage and calculate the deadtime to keep precise ZVS conditions.

In this article, static and dynamic measurements based on normally-off HEMTs with P-GaN technology are presented. This intends to highlight characterization boards for a half-bridge device composed of two GaN transistors integrated into one package. The first part describes boards which characterize the static behavior of the switching leg (I-V characteristics of the GaN component, RON parameter, parasitic capacitances, gate charge and charge values). The second part presents the dynamicresponse of a GaN transistor in ZVS application in terms of peak current, switching frequency and case temperature.

Dans cet article, nous presentons une technique de controle actif de grille pour maitriser la vitesse de commutation de transistors de puissance a semi-conducteur grand-gap. Un circuit de commande rapprochee innovant, permet de ralentir la vitesse de commutation a l'amorcage du transistor de puissance, reduisant ainsi les perturbations CEM, sans pour autant impacter trop lourdement les pertes de commutation. La methode proposee est implementee dans deux circuits integres en technologie CMOS qui permettent d'obtenir des temps de reaction pour une boucle de retroaction inferieurs a la nanoseconde. Avec de telles performances, il est montre experimentalement qu'il est possible de controler des vitesses de commutation superieures a 100 V/ns sous des tensions de 400 V.

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high dv/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and dv/dt can be actively controlled separately, and the tradeoff between the dv/dt and EoN switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from -175 to -120 V/ns for the 400 V application.

The objective of this work is to show the intrinsic limitations of a CMOS technology for the realization of an Active Gate Driver (AGD) with an active dv/dt control loop. Due to a theoretical study using first order models of CMOS submicron transistors, the main equations providing the link between feedback loop bandwidth and specific technology parameters are obtained. This optimization study allows us to determine the theoretical limits in terms of bandwidth and silicon area. Then, it becomes possible to determine the most appropriate switching control method to implement depending on the application requirements (high efficiency, low EMI), i.e. active feedback with adjustable gain, while ensuring suitable time delays. A feedback loop bandwidth of 1. 59GHz using a 1pF integrated capacitor to address a switching speed of 175V/ns is demonstrated. Experimental results and simulations using accurate technology models confirm the theory.

This paper presents an AGD (active gate driver) implemented with a low voltage CMOS technology to control the dv/dt sequence of low voltage (100V) and high voltage (650V) GaN power transistors. Such an AGD can control and reduce the dv/dt of fast switching GaN devices with a reduced impact on switching losses. In the case of both low voltage and high voltage GaN fast switching transistors, such an AGD must have a total response time lower than 1ns. Therefore, introducing a feedback loop to control the dv/dt requires a specific design with a very high bandwidth (550MHz). Moreover, probing the v(DS) voltage and its derivative is quite challenging, as the voltage level is higher than the low voltage gate driver supply. The purpose of this work is to optimize a low voltage CMOS AGD with fully integrated functions, and implement such a solution in GaN-based power converters.

In this paper, a CMOS gate driver in 180nm technology is presented. The gate driver implements an integrated and independent ultra-fast dV/dt control circuit dedicated to manage switch-on transients for GaN HEMT technology. In order to mitigate a detrimental effect in EMI spectrum for wide bandgap transistors, a novel method to reduce dV/dt without increasing so much switching losses is proposed. A comprehensive benchmark with the classical method is also presented, where the gate driver resistance is typically adjusted. Simulations are conducted to show the feasibility of the proposed method and the amount of switching energy that can be saved. Time responses of a feedback loop lower than 200ps are expected. The preliminary characterization of the integrated CMOS circuit is shown.