This paper presents theoretical analysis, closed-loop suppression design, and experimental verification of in-plane linear acceleration sensitivity in a center-anchor-supported quadruple-mass gyroscope (CSQMG). Despite the inherent common-mode rejection of multi-mass structures, capacitive nonlinearity and coupling electrostatic forces remain significant sources of g-sensitivity errors. A theoretical model considering capacitive nonlinearity in the sense electrodes and coupling electrostatic forces along the sense direction in the drive electrodes is developed for the CSQMG. Dedicated electrodes featuring a 45°-tilted comb design are implemented to suppress acceleration-induced displacement in a closed-loop feedback system. Experimental results demonstrate that the bias g-sensitivity is substantially reduced from 98.6°/h/g to 7.9°/h/g. Furthermore, scale factor g-sensitivity tests under centripetal acceleration show that the scale factor increment is suppressed from 0.27% to nearly zero. These results verify the effectiveness of the proposed closed-loop suppression technique for reducing MEMS gyroscope g-sensitivity, and further support the implementation of a novel single-drive six-axis integrated chip that combines a single-drive three-axis CSQMG and three-axis closed-loop accelerometers.

This paper presents an ultra-low-power wide-spectrum visible-infrared visual processing chip with on-chip energy harvesting scheme (VIR-EH) for always-on distributed vision sensor nodes. In VIR-EH, the inverter-based infrared read-out circuits and analog-digital hybrid near-sensor motion detection architecture are proposed to reduce the power consumption significantly. The power management unit (PMU) and energy scheduling strategy designed for on-chip energy harvesting enable the system to achieve ultra-low-power consumption. VIR-EH is designed in 180nm CMOS process and the simulation results show that the chip consumes 5.54 µW at a frame rate of 230 fps when executing motion detection task. The PMU of the chip can achieve an efficiency of 61.9% when supplying 795.4 nW of power to the system.

Analog compute-in-memory (ACIM) reduces data movement and leverages analog parallelism for efficient multiply-and-accumulate (MAC) operations. In charge-domain ACIM, grouped-row capacitors (GRC) and C-2C ladders have been proposed to execute one-shot multi-bit MACs, but practical implementations often suffer weighting imbalance and linearity loss due to unequal parasitics. This work presents a charge-domain multi-bit MAC macro with two circuit-level improvements. First, eliminating inter-group switches in GRC structure ensures that each bit-cell uses an identical input path, equalizing parasitics and improving activation weighting. Second, an asynchronous-sampling, synchronous-coupling signed C-2C ladder reduces top-/bottom-plate switching and ensures uniform output gain scaling, enhancing multi-bit weighting linearity. Implemented in 22nm CMOS, the macro performs one-shot 4W4A MAC operations. Post-layout simulations show excellent linearity (DNL < 0.10LSB, INL < 0.41LSB), achieving 283.2TOPS/W and 2.73TOPS/mm2.

This paper proposes a chopper operational amplifier with low input-referred noise and low input offset voltage. By adopting an auto-correction feedback (ACFB) loop to reduce the input offset voltage in the DC domain, output ripple is suppressed at the source, avoiding additional noise introduced by subsequent filtering. An adaptive clock bootstrap circuit is also employed to provide a constant overdrive voltage to the chopper switches, reducing the effects of charge injection, improving Common-Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio (PSRR), and enabling the circuit to achieve rail-to-rail input. The amplifier is implemented using a 180 nm CMOS process, operating with a supply voltage of 3.2 V to 5.5 V, and consuming 838.3 μA of current. Post-layout simulation results show that the amplifier with an input-referred noise of 9.55 nV/√Hz@1Hz, an 0.1–10 Hz input-referred peak-peak noise of 0.62 μVₚ₋ₚ and an input offset voltage of 3.3 μV. Its CMRR is 134 dB, and its PSRR is 127 dB, demonstrating excellent high-precision performance.

Smart sensing is an emerging technology that enables real-time intelligent decision-making directly at the data source. However, smart sensors typically face difficulties in the deployment of complex algorithms, such as large convolutional neural networks (CNNs), owing to a restricted power and area budget. Although analog computing-in-memory (CIM) has made great strides in these areas, a major remaining cost of energy and area stems from partial sums (pSUMs) and their associated digital circuitry. This brief presents Shuffle-CIM, a CIM architecture that incorporates the shuffle scheme and analog non-multiply-and-accumulate (non-MAC) implementation. The shuffle scheme eliminates the need for pSUM accumulation, and without pSUM constraints, a specialized ReLU-ADC design integrates non-MAC computations directly into the analog domain, achieving an all-analog CIM macro. Implemented on TSMC 40nm, the Shuffle-CIM design achieves a power consumption of 4.90mW and an area of 0.396mm2, representing a 3.1x and 2.9x reduction compared to the conventional CIM architecture. The resulting energy efficiency and area efficiency reach 107.55TOPS/W and 1.33TOPS/mm2, with an accuracy of 89.01% on CIFAR-10.

This work proposes, for the first time, a novel assembly-free electrode design for micro hemispherical resonator gyroscopes ($\mu$-HRGs), along with an integrated process for the simultaneous fabrication of both the resonator and electrodes. The resonator and electrodes are co-fabricated in a single high-temperature molding process of two layers of fused silica, with the electrode-resonator gap precisely defined by the thickness of a pre-deposited metal layer prior to molding process. A temporary electrode interconnection structure is designed to mechanically connect the resonator and electrodes during fabrication, maintaining their relative alignment. After metallization of both the resonator and electrodes, the electrode interconnection structure is selectively removed by laser cutting to electrically isolate the resonator from the electrodes. The fabricated device achieves a total capacitance of 16.06 pF across 16 electrodes, providing a large drive and sense capacitance while eliminating the need for complex assembly processes.

This article shows the design, fabrication, test verification, and theoretical analysis of a proposed sandwich wafer-level packaging (WLP) structure with double-sided out-of-plane electrode configuration and precise symmetry adjustment method of 5-mu m out-of-plane gaps for micro-electromechanical system (MEMS) devices requiring control and detection of out-of-plane movement. Common WLP schemes are typically fabricated based on the silicon-on-insulator (SOI) process and direct silicon bonding, which makes it difficult to place double-sided out-of-plane electrodes. In this article, a glass-silicon-glass sandwich WLP scheme is designed to configure symmetrical out-of-plane electrodes on top and bottom layers. Anodic bonding and Au-Sn solid-liquid interdiffusion (SLID) bonding are used for the WLP encapsulation of triple stacks. Gaps between out-of-plane electrodes and suspended mass are controlled by the height of etched silicon anchors and standoffs. Extremely thin metallization layers with a total thickness of less than 3 mu m are precisely deposited by a novel online calibration method to reach the required Au-Sn composition for a stable liquid phase transition during bonding, matching standoff height for out-of-plane gap control. After fabrication, capacitance is measured to evaluate the double-sided symmetry of the out-of-plane electrode gaps. WLP dies with standoffs have a relative capacitance difference of less than 1.77%, while WLP dies without standoffs have a relative capacitance difference of 7.82%. A theoretical symmetry analysis based on process data is carried out to resolve capacitance variance into several sources, achieving a high estimation accuracy of 87.6%. The designed WLP framework is aimed at a fabrication implementation based on universal MEMS processes, without a requirement for an advanced MEMS platform.

This letter presents a quantitative approach for 2.5 mu m Au-Sn metallization with accurate mass calibration, which is applied to solid-liquid interdiffusion bonding of microelectromechanical systems (MEMS) wafer-level packaging (WLP) devices, particularly those that demand a micron-level gap of out-of-plane electrodes. For Au-Sn metallization, traditional deposition methods, such as electroplating, are unable to achieve micron-level thickness and accurate composition due to poor robustness to varying process conditions. In this study, we further improve the composition of the deposited Au-Sn alloy through direct mass measurement and calibration during the cosputtering process. In the experiment, a high-precision balance with a resolution of 0.1 mg was utilized to measure the mass increment of sputtered Au and Sn in the clean room. Subsequently, the sputtering rate of the Sn target was calculated and applied to calibrate the final Au-Sn composition. According to the energy-dispersive X-ray spectrum (EDS) results, the difference between the measured Au-Sn mass composition and the set value is 1.1%, which is significantly lower than the typical 5%-10% composition deviation of electroplated Au-Sn solder, demonstrating a strengthened robustness to varying conditions by the effective calibration. The test results show that the shear strength of the WLP structure reaches 31.8 MPa, and the cross-sectional EDS results of the as-bonded Au-Sn alloy are consistent with the designed Au-Sn composition. The proposed calibration method can also be applied to other alloy depositions that require precise mass composition and micron-level thickness with a better robustness to varying conditions.

This paper presents a high-energy-efficiency infrared near sensor architecture chip for infrared intelligent sensing, which adopts inverter-based capacitive transimpedance amplifier(IB-CTIA) and correlated double-sampling multiply-and-accumulation(CDS-MAC) technologies. In 180nm CMOS, the proposed architecture under 1.8V consumes 129 $\mu$ W (active)/75 $\mu$ W (idle) with a frame rate of 155fps and a recognition accuracy of 91.8% on MNIST dataset classification task, enabling its efficient deployment of infrared intelligent in edge sensing.

In the natural world, energy and information are deeply entwined, mutually constraining and complementing each other. To exploit this natural merit, this paper proposes a FEI strategy: Fusion processing of sensing Energy and Information for infrared smart vision system. The proposed Information-Power-Coupler (IPCp) takes the ability of simultaneous energy harvesting and low power inpixel computing, which utilizes in-situ coupled energy to process the containing information on the same focal plane. Furthermore, a self-adaptive Intelligent-Power- Controller (IPCtrl) capable of scheduling the harvested energy to complete low power neural network inference is introduced. The implementation of IPC2 system utilizes a software-hardware co-design strategy to exploit the layer-wise characteristic of the computation process and circuit topology, achieving energy-efficient self-sustainable fusion processing of sensing energy and information. Simulation results show that the IPCtrl could supply 594.68nW with the power conversion efficiency of 93.38%, when the harvested energy from the IPCp is 636.84nW. The performance validates the self-sustainability of the system with the self-powered image recognition of a complete network running at 4fps with an accuracy of 99.4%.

Addressing the need for intrusion detection and localization in critical areas, this study develops a method for outdoor ground vibration source localization utilizing subterranean-deployed MEMS accelerometers. First, the Particle Swarm Optimization (PSO) algorithm is employed to minimize the Geometric Dilution of Precision (GDOP), thereby determining the optimal configuration of the sensor array. The acquired signals are then filtered, and a novel time delay estimation algorithm, termed the Sliding Window Derivative (SWD) algorithm, is proposed. This method utilizes a sliding window to compute the sum of squared differences between adjacent sampling points within the window, generating a time-windowed energy change signal. The derivative of this signal yields a rate-of-change curve, highlighting abrupt signal transitions. The SWD algorithm, in conjunction with the STA/LTA–AIC algorithm, precisely identifies the first arrival point of the vibration signal, determining its time of arrival at each of the four sensors. Finally, an improved two-step weighted least squares method based on Time Difference of Arrival (TDOA) is used to calculate the position of the vibration source. Experimental results demonstrate an average positional error of 0.095 m and an average directional error of 0.935 degrees, validating the efficacy of the proposed method in achieving high-precision localization in outdoor environments.

In an increasingly interconnected world, flexible wearable systems have emerged as transformative technologies, revolutionizing the monitoring and management of personal health and daily activities. With the surging demand for health monitoring, these systems have demonstrated remarkable potential in heart rate monitoring and the detection of heart rate irregularities. This paper provides a comprehensive review of the design of flexible wearable heart rate monitoring systems, with a particular focus on their low-power design. The low-power design is reviewed from four constituent modules of the system, namely the heart rate signal acquisition module, preprocessing module, computation module, and transmission/output module. Meanwhile, for each module, low-power design strategies are reviewed from three different dimensions: hardware-level optimization, algorithm-level enhancement, and hardware–algorithm co-design approaches. Through this multi-dimensional review, the importance of low-power design in flexible wearable heart rate monitoring systems is emphasized. In addition, this paper offers a perspective on the future of low-power design for flexible wearable heart rate monitoring systems. With the advancements in materials science and flexible electronics technology, it is believed that there will surely be better design methods and strategies for the low-power design of flexible wearable systems.

Compute-In-Memory (CIM) has emerged as a promising solution to address the von-Neumann bottleneck, making it a key technology for intelligent computing in edge IoT devices, particularly for real-time applications like keyword spotting (KWS). However, traditional CIM architectures face challenges such as high resource consumption, especially in data conversion, which can significantly impact chip area and energy efficiency. To address these challenges, this work proposes a computational CIM architecture utilizing multilevel analog memory, named AM-CIM, tailored for near-sensor (NS) computation of real-time KWS applications. Additionally, approximate memory technology is integrated into the AM-CIM architecture, employing data resilience scheduling for analog memory which contributes to significant reductions in hardware overhead. This integration facilitates a hardware-software co-design approach. To deploy KWS tasks in AM-CIM, a gated recurrent unit (GRU) network, referred to as MAC-GRU, is implemented. By employing Mel-energy as the input feature at the near-sensor end, the system achieves a 93.13% reduction in feature extraction power consumption. Evaluation results based on TSMC 180-nm technology demonstrate that the AM-CIM architecture achieves an accuracy of 88.51% for 10-keyword classification with a power consumption of 546 mu W, while reducing analog memory area by 43.32%.

This paper describes a three-layer wafer-level package (WLP) scheme with lateral feedthrough signals and double-sided symmetrical out-plane electrodes for 3D MEMS devices. The WLP usually adopts the lateral signal routing scheme under the insulating layer or the vertical routing scheme based on TGV and TSV processes. SOI processes cannot easily place out-plane electrodes under the device layer. Therefore, a WLP scheme based on the SOG process and lateral signal routing is proposed and verified. The fabrication sequentially adopts anodic bonding and Au-Sn solid-liquid interdiffusion (SLID) bonding to realize the encapsulation of a stack of three layers and gap control of symmetrical out-plane electrodes by anchors and standoffs on device layer. Considering that the signal leads arranged under the insulation will face the risk of failure due to bonding pressure, this paper designs a novel signal lateral feedthrough scheme to improve the process yield. Shear strength test shows an average shear strength of 18.5MPa. Capacitance measurement is done to evaluate fabrication accuracy of out-plane electrodes. 8 dies from first fabrication flow have an average capacitance dispersion of 8.9%.

This paper presents a Spread spectrum clock oscillator for the DC-DC converter. In this design, digital logic control is added based on the RC relaxation oscillator, which makes the charging and discharging current of the oscillator change randomly in the set range. This random change of current can achieve the corresponding spread spectrum to achieve the purpose of reducing EMI. In addition, this oscillator design can achieve four different operational modes through the external control signal: 7 -bit output mode and 8 -bit output mode without spread spectrum, 7-bit output mode and 8-bit output mode with spread spectrum. The simulation results show that the oscillating frequency of the oscillator is 16.7MHz without the spread spectrum under 7-bit output mode, after spreading spectrum, the depth of spread spectrum is $54.4 \%$, which the peak energy is reduced by 24dB compared with that before spreading spectrum. Under 8-bit output mode, the oscillator oscillates at 19.6MHz without spreading spectrum, after spreading spectrum, the depth of spread spectrum is $58 \%$ with the 22dB peak energy reduction.

A high-precision capacitive absolute angle sensor with improved temperature performance is presented. The proposed sensor comprises a rotor and a stator. Two opposing excitation signals are applied to the excitation electrodes of the stator. The contour of the sensitive structures is designed and optimized in order to ensure that the DC values of the obtained capacitance signals are as close to zero as possible. Consequently, the utilization of the capacitance cancel array, which would introduce temperature instability, is avoided. The full-temperature performance tests are conducted on the prototype. The result reveals that the resolution is and the maximum measurement error over the full range is under -45 degrees C similar to+65 degrees C, showing the potential of the proposed prototype to achieve high-precision measurement over the full temperature range.

In order to reduce the storage space occupied by the well-trained Keyword Spotting (KWS) network model during deployment on terminal devices while maintaining the recognition accuracy of the model as much as possible, a new method of 'peak' quantization is proposed. By limiting the maximum value of the network model weights to change the quantization process, it has achieved good results in reducing the loss of recognition accuracy. Compared with other Network quantization, such as traditional quantization and Alternating Direction Method of Multipliers (ADMM) quantization, it shows the advantages and characteristics of 'peak' quantization. Through related experiments with the Google voice dataset and the MNIST dataset, its universality is demonstrated.

This paper proposes an ultra-low-power CMOS Image Sensor (CIS) chip based on sensing-with-computing (Senputing) architecture to reduce the power bottleneck of vision system. This Senputing chip achieves BNN 1st-layer convolution in analog domain with ultra-low power consumption. It has two working modes, Normal-Sensor (NS) mode and Direct- Photocurrent-Computation (DPC) mode. The prototype measurement results under 65nm CMOS process on MNIST classification task shows that the power of feature map computation is 2.17μW with 120fps frame rates and 98.1% accuracy. The computation efficiency reaches to 11.49TOPs/W, which is 14.8× higher than state-of-art works.

This paper presents a low-noise low-input base current amplifier with both low-voltage and high voltage output capability. The amplifier has low frequency noise and input base current by employing a BJT input stage with a novel base current compensation structure, and has low and high voltage output capability by setting the input stage of it at low voltage supply (VDDL), the third and the output stage at high voltage supply (VDDH). Simulation results show the input base current of the amplifier is around 0.1nA, and the temperature coefficient of input current is around 6pA/°C over −45°C to 125°C, the equivalent input noise of the amplifier is 5.3nV/rt Hz at 1Hz, 8.2nV/rt Hz at 0.001Hz, and the output voltage range can be from 4V to 50V with VDDL=5V, VDDH=55V. The current consumption of the amplifier is 150$\mu$A with VDDL, 450$\mu$A with VDDH. Besides, with capacitor load condition of 20pF, the bandwidth of the proposed amplifier is 24MHz, the slew rate is 11. 29MV/s. The amplifier is implemented in 180 nm BCD process. It occupies an active area of 0.504mm 2 .

This paper presents a single-excitation absolute capacitive rotary encoder that is small in size, lightweight, robust, and highly precise. The encoder consists of two plates: a rotor and a stator. The rotor consists of a planar coupling ring, a petal-form sensitive electrode, and a rough sensitive electrode, whereas the stator consists of a planar excitation ring and eight groups of collection electrodes. First, the two sensitive electrodes together with the eight sets of collection electrodes encode the angular position into amplitude-modulated signals, which are read out by a single-excitation electronic system. High-precision absolute position information is obtained by using the combination of 36 petal-form sensitive electrodes and a rough sensitive electrode. Then, a linear programming method is used to optimize the critical dimensions of the encoder within a limited area to achieve a miniaturized design. Finally, a harmonic frequency compensation method is used to reduce repeatable and periodical measurement errors, which are caused by manufacturing, circuit, and installation errors. A prototype is fabricated and tested on a high-precision testing turntable. The measurement results show that the resolution is 0.00015° and the accuracy over the full absolute range is 0.0022°, indicating that the encoder has considerable potential for use in high-precision applications.