Negative Bitline (NBL) write-assist techniques are widely used to improve write-ability and write yield in SRAM. However, these techniques often lead to increased power consumption during write operations. The present work focuses on optimizing the NBL scheme to achieve reliable low-voltage operation with improved energy efficiency. Foot Switch PMOS Access Voltage Latch Sense Amplifier (FSPA-VLSA) enables power-efficient and reliable read sensing. NBL circuit is systematically analyzed using three capacitance configurations controlled by the coupling signal for FSPA-VLSA. The coupling signal and delay unit settings are adjusted to determine the optimal configuration for minimal operating voltage and reduced power consumption. To validate the proposed approach, extensive simulations are carried out across process corners, supply voltage variations, and a temperature range from -20°C to 85°C. The results demonstrate that the proposed configurations provide stable operation and enable efficient functionality down to a scaled supply voltage of 0.75 V, making the design suitable for low voltage and low-power SRAM applications.

This paper presents a comprehensive study of the 6T, 8T, 9T and 10T Static Random Access Memory (SRAM) bitcells for In-Memory Computing (IMC) under the various storage-node patterns (viz. 00,01,10,11) using a 180nm CMOS process. Results show that IMC behavior is strongly data dependent. For the 01/10 conditions, the 6T cell exhibits the lowest delay but suffers from significantly higher total power dissipation compared to the other architectures, while the 9T and 10T cells maintain balanced delay and substantially lower power. Under the 00/11 patterns, the 8T cell records the highest total power dissipation, whereas the 6T, 9T and 10T cells demonstrate nearly similar and much lower power dissipation. Two of the low-power design techniques (namely, transistor stacking and dual-level voltage scaling) are applied across all architectures. These techniques reduce power in every SRAM cell. However, the relative trends remain consistent, with the 6T cell still consuming the highest power for 01/10 and the 8T cell for 00/11. Although delay increases for all the cells due to both low-power techniques, the overall energy efficiency improves. Power-Delay-Product (PDP) analysis confirms that the 10T cell achieves the best PDP across all conditions, making the 10T architecture the most energy-efficient and reliable candidate for low-power IMC applications.

The stability and yield of Static Random Access Memory (SRAM) are significantly impacted by process, voltage, and temperature (PVT) variations in deep-submicron technologies. These PVT variations can be accounted in EDA tools using SPICE simulations. While conventional Monte-Carlo simulations offer accurate yield estimation, they are computationally intensive and time-consuming. The present work focuses on a variation-aware Machine Learning framework for a 6T SRAM cell designed in Cadence Virtuoso in 45nm technology node. A large number of Monte-Carlo simulations are performed by sweeping transistor widths, process corners, and temperature conditions to attain the dataset for training ML model. The proposed ML model is able to quickly predict SRAM performance parameters including read Static Noise Margin (RSNM), write SNM (WSNM), hold SNM (HSNM), access delay, and leakage power from 3,751 simulation samples using Gradient Boosting regression. The present work enables fast and accurate estimation of parametric yield while significantly reducing reliance on repeated SPICE level Monte-Carlo simulations with more that 95% of accuracy in each of the parameter. The generated dataset forms the basis for a machine learning based prediction framework. The results demonstrate that data-driven models can effectively capture nonlinear PVT dependencies and provide a scalable solution for early-stage SRAM design optimization.

Differential power analysis (DPA) stands as a formidable threat to cryptographic systems, exposing vulnerabilities in secure implementations and posing significant risks to sensitive information. Device power usage observations reveal details about the functions a device performs as well as the data it is processing. Substitution-box (S-box) circuits are employed to determine the relationship between cipher information and secret keys. However, because of more usage of power, attackers using DPA can exploit the S-box. In this paper, a secured and energy-efficient S-box circuit is implemented and proposed using CMOS transmission gate (TG) logic, and it is verified that it is DPA-resistant. Results reveal that CMOS TG-based S-box circuit occupies less area, dissipates less energy and requires lower power consumption in contrast to the standard CMOS and other existing logic families that are resistant to DPA attack. Security parameters, viz., normalized energy deviation and normalized standard deviation values obtained reveal that the power consumption values are uniform, and the circuit is resistant against DPA attack, making it suitable for use in various applications like smart cards, sensors, hardware IoT devices, etc. Cadence EDA tools have been used for designing of S-box circuit using a 180 nm CMOS technology node.

A Phase-Locked Loop (PLL) is an important negative feedback closed loop electronics circuit which facilitates locking the phase of its output to an input reference signal. The functional components of PLL consist of Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF) and Voltage Controlled Oscillator (VCO). This work presents a comparative analysis of different VCO architectures for PLL systems. Three VCO topologies, namely, Ring oscillator, Current- Starved Ring oscillator (CSRO), and LCTank oscillator are considered in the present study. The designs are implemented using a 180 nm CMOS technology node. The key performance metrics includes lock time, settling time, jitter and power efficiency are assessed. The results reveal that the LC Tank oscillator exhibits fast lock and settling times but suffers from power consumption. The CSRO design offers a balanced trade-off between power and frequency stability, making it a more versatile choice for modern communication systems. The implemented circuits are significantly advantageous for various communication and signal processing applications.

In the present paper, a new 1-bit hybrid full adder has been designed and proposed. The adder essentially consists of two modules, a 2-input exclusive-OR/exclusive-NOR gate, and a 2:1 multiplexer. The circuit performance is analysed in terms of metrics namely, power usage, transistor count, power-delay product (PDP), driving capability, and power-delaynumber of transistors product (PDNP). Simulative analysis using Tanner EDA tools for CMOS 45 nm technology node shows that in comparison to prior hybrid full adder (HFA) designs, the suggested design offers superior space demand and power. The proposed circuit is also analysed with temperature variation and voltage scaling, to study its performance under varying conditions. In comparison to the existing one-bit hybrid full adder circuits, simulative analysis demonstrates that the proposed design displays lower power consumption, and lower PDNP value, thus is both energy and area efficient.

The integrity of a signal through a via depends upon the electrical characteristics of the substrate and the filler materials in 2.5D/3D VLSI chip. Through-glass-vias (TGVs) provide a vertical interconnection through the glass interposer. The present paper suggests a differential multibit TGV wherein glass is used as substrate material filled with carbon nanotubes (CNTs). Glass offers higher electrical resistivity. The proposed structure of cylindrical TGV is such that one layer of multiwalled CNTs (MWCNTs) is added on the periphery and single walled CNTs (SWCNTs) are filled in the core. The behavior of the proposed structure at high frequencies is studied by computing its effective complex conductivity. The modeling of electrical equivalent model of TGVs is the same as that of the transmission line model of electrical circuits wherein the parasitics of the circuit such as resistance, capacitance, conductance, and inductance are distributed throughout the path. These frequency-dependent parasitics are determined using the partial-element equivalent circuit (PEEC) technique and validated with ABCD matrix technique for different geometrical parameters. The conductivity, resistance, capacitance, and inductance offered by the TGV are studied. It is further analyzed that increasing the number of conducting channels increases conductivity. The proposed structure provides less resistance, making it a more efficient design.

Fractal structures have brought forth the seamless emergence of wireless devices wherein every constituting component of the integrated radio frequency front-end circuitry is getting miniaturized. Fractal antennas offer solutions of not just the size reduction but also provide multiple resonances with wide or broad or ultra-wide impedance bandwidth, and high gain response. These antennas do not require additional loading components which lead to ease in the fabrication process. Despite numerous benefits, fractals find limited application because of the conventionally slow process that is involved in their development. Artificial intelligence (AI) algorithms aid in skipping one or more stages and boosting the overall design procedure. Not much is available in the literature on implementing these methods to design fractal antennas for multiple requirements. The purpose of the present work is, therefore, to provide a comprehensive review of the various categories of fractal structures in electromagnetics that have been exploited by the modern-day antenna technology to serve the numerous applications. The theory and analysis techniques and the existing state-of-the-art works of the commonly used fractals, viz., the Koch, Minkowski, Hilbert, Trees, and the Sierpinski class have been reviewed in this manuscript. The present study shall leverage meaningful data insights into the fractal philosophy which would help the antenna engineers to rapidly facilitate custom antenna prototypes for their global clients by using AI techniques.

In the present paper, a 1-bit hybrid full adder (HFA) is designed and presented. The HFA essentially consists of two modules, a 2-input exclusive-OR/exclusive-NOR gate, and a 2:1 multiplexer. The proposed circuit has a performance upper edge in terms of metrics namely, power usage, transistor count, power-delay product (PDP), driving capability, and Power-delay-number of transistors product (PDNP). Simulative analysis using Tanner EDA tools for CMOS 45 nm technology node shows that in comparison to prior HFAs reported in the literature, the suggested circuit offers superior space demands and power. The proposed circuit is also analyzed with voltage scaling, and it is found that it offers the best performance at 1.2 V supply voltage. Compared to current one-bit hybrid full adder circuits, simulation findings demonstrate that the suggested design displays lower power consumption, lower PDP, requires fewer transistors, and lower PDNP value.

Field programmable gate arrays (FPGAs) and advanced embedded computing boards have become essential to attain high performance in modern computing systems. This offers substantial control capability, improves productivity and efficiency across various applications. The current work incorporates audio processing and denoising using accelerated computing. The coefficients of the infinite impulse response (IIR) filter are fine-tuned to get optimal results. The audio signal comprises 64,000 samples, each with 16-bit resolution, having a sampling rate of 16 kHz. The audio processing using Verilog has been executed on two different platforms: the first is a general-purpose computer, and the second is an FPGA. It has been observed that audio processing on an FPGA-based platform offers higher computational efficiency. This can be good in handling real-time, computation-intensive digital signal processing (DSP) applications, such as image and audio denoising, and machine learning, where both performance and resource utilization are critical.

In this paper, we have proposed the precise model of coaxial TGVs (CTGVs) which consists of ground-signal signal-ground (GSSG) TGVs. An equivalent electrical model of CTGVs is established and the partial element equivalent circuit (PEEC) technique is used to extract the frequency-dependent impedance parameters. In CTGVs, multi-walled carbon nanotubes (MWCNT) and copper is used as filler material in inner and outer layer. Resistance and inductance of CTGVs is calculated using the PEEC technique for different filler materials. The insertion loss (S21) of CTGVs is determined using the HFSS simulations and is compared analytically in differential mode configurations. S21 is calculated for various geometrical parameters of MWCNT-based CTGVs such as diameter of TGV, pitch between CTGV pair, as well as material properties such as permittivity of SiO2 and benzocyclobutene (BCB) polymers. It is established that MWCNT based CTGV shows improved insertion loss because the conductivity of MWCNT is higher in comparison to copper.

In the realm of high-frequency three-dimensional integrated circuits, performance of through-glass vias (TGVs) is of significant concern. Through recurrent neural network (RNN) technique, this paper presents an innovative approach of signal integrity analysis for coaxial-TGVs. This technique leverages the temporal dependencies of electromagnetic fields within coaxial-TGVs and effectively captures the intricate interactions that cause crosstalk. By training the RNN on the TGV dataset, a more accurate and adaptable crosstalk prediction in coaxial-TGVs has been achieved.

Speech coding is a widely used technique used for digital telephony and secure communication. The estimation of linear prediction coefficients (LPCs) for the development of synthetic speech is crucial and involves the use of the Levinson–Durbin (LD) algorithm. The computational complexity introduced by this algorithm affects the performance of speech codecs utilizing LPCs. In this paper, an FPGA implementation of the Levinson–Durbin algorithm is proposed for efficient autoregressive model parameter estimation. By harnessing FPGA’s parallel processing capabilities, the algorithm’s performance is accelerated, allowing real-time processing of signals. The work focuses on translating the algorithmic steps into hardware modules, optimizing memory access, and evaluating resource utilization, and power efficiency of the implemented hardware. This research contributes to the field of hardware-accelerated algorithms, showcasing the potential of FPGA platforms in enhancing signal processing tasks.

A voltage-controlled oscillator (VCO) is a pertinent constituent of numerous electronics gadgets in the present era. VCOs are used in a variety of applications, namely frequency synthesizer, function/signal generator, keypad tone recognizer, building of PLL and various other areas. The implementation and analysis of a VCO having high-frequency and low-power dissipation is presented in this study. The design employs current-starving technique, in which the amount of current for each inverter stage is limited. This technique helps to control power consumed by VCO and provides an efficient tuning of VCO oscillation frequency. The presented VCO provides an output frequency ranging from 749.07 MHz to 2.41 GHz when operated at 1.8 V supply voltage and consumes a total power of 1.5 mW. Tanner EDA tools have been used to analyse and implement the VCO design for the 180 nm CMOS technology node.

In the present manuscript, inverse artificial neural network methodology has been used for the rapid design of the multi-frequency antenna structures to facilitate multiple custom requirements. In the first stage, the performance parameters, viz., the frequencies and the associated voltage standing wave ratios/return losses/bandwidths, and gains/directivities of the candidate multiband antenna structures, have been fed as inputs to the inverse models through independent neural network branches. The outputs of the different branches have been then integrated using an extreme learning machine in the second stage, and the corresponding design parameters of the antennas have been obtained at the model output. Upon successful evaluation, the proposed models have been implemented for practical applications. The performance of the developed models has been found to be superior to the traditional inverse extreme learning machine models and various other state-of-the-art artificial intelligence models reported in the literature. The presented work is a significant effort to broaden the scope of designing rapidly the multiband antennas beyond that for custom frequencies and shall rapidly facilitate several user-specific electromagnetic responses in multiband applications.

In speech coding, denoising of the speech signal is essential as well as crucial. The filters for minimizing errors through denoising employ the autoregressive moving average (ARMA) approach, introducing higher computational complexity in speech coder design. This research work presents the design and implementation of an effective perceptual weighting filter (PWF) for speech coding. The high-level synthesis of the fixed-point PWF filter is optimized by multiple optimization techniques along with detailed design space exploration using the weighted sum (WS) method. To enhance the performance, an FPGA-based hardware accelerator is proposed using hardware/software (HW/SW) co-design in an embedded environment. Simulative analysis in Vivado HLS and final accelerator design in the Vitis IDE tool validate the proposed architecture by using real-time speech samples, demonstrating a 50% reduction in area and a 99% execution improvement. This makes it well-suited for use in modern speech codecs, enhancing the efficiency.

Antennas are used by modern communication systems for a variety of purposes. Multiband antennas are proving versatile for most systems because of their efficient multi-functional services. The methods of slotting, defected grounds, stacking, metamaterials, reconfiguration, etc., which have been used over a long span of time to enable multi-frequency operation in antennas, have their own constraints. The Sierpinski Gasket fractal antennas are potentially the strongest contenders for implementing rapid multiband antenna design. This is because the multiple frequencies of these antennas result from the geometric self-similarity property of fractal, and can be influenced by the geometric parameters of the Gasket fractal. Plethora of investigations is reported in the literature on the scaling of Gasket height to generate multiple frequencies. Limited research is, however, available on the contribution of the flare angle design parameter of Gasket structures. Also, for practical applications, frequency is only one of several antenna-parameters, namely, return loss, bandwidth, gain, directivity, etc., that are required to be customized. In fact, using ways to quickly design Gasket antennas for multiple requirements would necessitate controlling reflection and radiation properties as well, which are associated with the antenna frequencies. In view of these concerns, the various transmission line feeding configurations of Gasket antennas have been explored in the current research effort to ascertain the contribution of various design characteristics that regulate the overall performance of these antennas. The novel insight presented into the establishment of input–output pairs of Gasket fractal antennas shall expedite the development of antennas with custom multiband properties.

Linear prediction analysis is a crucial technique used in speech coding to compress speech signals and facilitate their reliable transmission over limited bandwidth or storage space. However, this technique involves repetitive computations on a wide range of incoming audio data, leading to high resource consumption and execution time. To address this challenge, an FPGA-based acceleration method is proposed in the present work that provides high computational capabilities and is energy efficient. The study focuses on optimizing linear prediction analysis at the sub-block level, specifically by modifying the autocorrelation and Levinson–Durbin algorithm to enhance the performance of the overall system. The suggested algorithm is integrated into a hardware/software co-design as a high-performance intellectual property with an AXI4-Stream interface. The system achieves over 99% speed increase and a 60% reduction in resource utilization, by the proposed hardware acceleration implementation. These findings are significant for designing optimized hardware for low bit rate speech coders with improved execution time and reduced resource consumption. The approach is validated by simulating and testing the complete system-on-chip architecture on a Zynq Zybo FPGA for functionality and real-time data performance.

In this paper, signal integrity assessment is carried out for graphene nanoribbon field effect transistor (GNRFET) based ternary logic with dielectric inserted multi-layered GNR (MLGNR) interconnects. The analyses are carried out for crosstalk effects and eye diagrams with and without shielding lines. In this paper firstly, it is observed that the dielectric inserted MLGNR interconnects show better than copper (Cu) and multiwall carbon nanotube (MWCNT) interconnects. Secondly, active shield technique is adopted, and observed that it exhibits better performance than without shield and passive shield techniques. Also, the power-delay product performance parameter is evaluated and envisaged that active shield technique outperforms passive technique. Further, the eye diagram analysis is carried out for different bit rates. The different performance analyses in the paper have been carried out for 10 nm technology node.