Heterojunction solar cells were fabricated by electrochemical deposition of p-type, cuprous oxide (Cu2O) absorber on sputtered, n-type ZnO layer. X-ray diffraction measurements revealed that the as-deposited absorber consists mainly of Cu2O, but appreciable amounts of metallic Cu and cupric oxide (CuO) are also present. These undesired oxidation states are incorporated during the deposition process and have a detrimental effect on the photovoltaic properties of the cells. The open circuit voltage (VOC), short circuit current density (jSC), fill factor (FF) and power conversion efficiency (η) of the as-deposited cells are 0.37 V, 3.71 mA/cm2, 35.7% and 0.49%, respectively, under AM1.5G illumination. We show that by thermal annealing in vacuum, at temperatures up to 300 °C, compositional purity of the Cu2O absorber could be obtained. A general improvement of the heterojunction and bulk materials quality is observed, reflected upon the smallest influence of the shunt and series resistance on the transport properties of the cells in dark and under illumination. Independent of the annealing temperature, transport is dominated by the space-charge layer generation-recombination current. After annealing at 300 °C the solar cell parameters could be significantly improved to the values of: VOC = 0.505 V, jSC = 4.67 mA/cm2, FF = 47.1% and η = 1.12%.

Y2O3 and L2O3/ZrO2 stacks have been examined in terms of their electrical properties in Ge capacitors. It is discussed that scaling of L2O3/ZrO2 stacks into the sub 1 nm EOT regime can be achieved either by using thin amorphous La2O3 capped by a thin ZrO2 layer or by stabilizing the tetragonal or cubic very high-k phase of ZrO2 induced by diffused La and Ge atoms during a PDA step. Y2O3 shows very good interfacial qualities in terms of a low interface trap density and hysteresis when an annealing in O2 atmosphere is applied. Fowler-Nordheim tunneling is identified as the primary leakage current mechanism at high gate bias whereas for the low bias regime leakage current is primary conducted by direct tunneling through the Y2O3 layer.

Various metal oxides are probed as extrinsic thin tunnel barriers in Semiconductor Insulator Semiconductor solar cells. Namely Al2O3, ZrO2, Y2O3, and La2O3 thin films are in between n-type ZnO:Al (AZO) and p-type Si substrates by means of Atomic Layer Deposition. Low reverse dark current–density as low as 3×10−7 A/cm2, a fill factor up to 71.3%, and open-circuit voltage as high as 527 mV are obtained, achieving conversion efficiency of 8% for the rare earth oxide La2O3. ZrO2 and notably Al2O3 show drawbacks in performance suggesting an adverse reactivity with AZO as also indicated by X-ray Photoelectron Spectroscopy.

In this work, we report on the fabrication, characterization, and photovoltaic properties of sputter-deposited, thin film heterojunctions combining p-type cupric oxide (CuO) absorber with n-type ZnO. The structural investigation reveals highly crystalline, columnar growth of the layers and confirms that the absorber's phase is purely CuO, with only negligible traces of Cu2O. The optical characterization yields for CuO an indirect bandgap of 1.2 eV and a direct optical transition at approximately 3 eV. The short circuit current, open circuit voltage, fill factor, and power conversion efficiency of the heterojunction solar cells were extracted as a function of the CuO thickness under AM1.5 G (1 kW/m2) illumination. From the observed dependencies, we conclude that the photovoltaic performance is compromised by a restricted carrier collection efficiency, caused by the small carrier lifetime in CuO. Indeed, the carrier population is found to decay with time constants of 40 and 460 ps. A maximum power conversion efficiency of 0.08% was obtained for the solar cell with CuO thickness of 500 nm.

Next generation thin film photovoltaics actually face several great challenges: they have to compete with wafer-based silicon based modules in terms of efficiency, costs and production volume. In order to succeed at the market in the long term, they may need to achieve conversion efficiencies of beyond 15%, and contain solely abundant and non-toxic materials within reliable and ideally flexible modules. CZTS based solar cell technology is currently maybe the most promising approach in order to meet these requirements in the near future. Solution processed CZTSSe laboratory-scale solar cells currently exhibit the highest conversion efficiencies of above 11% for this technology. Nevertheless, the material is still in an R&D stage, implying open questions regarding crystal structure, defects, composition and superior device structure.Several recent publications on CZTS give excellent reviews from basic material questions to device processing subjects. The scope of the present work is to interrelate these issues with the actual and projected medium and long-term manufacturing development and market situation. This shall elaborate relations between market demand and constraints, technology and manufacturing challenges and potentials, as well as (raw) material costs and utilization. Finally, the question is being addressed whether solution processed technologies - in particular CZTS - offer the potential to fabricate next generation thin film devices that are marketable in terms of conversion efficiency as well as sustainable, cost-effective, high-throughput production. (C) 2013 Elsevier Ltd. All rights reserved.

Highly ordered arrays of silicon nanopillars are etched by means of induced-coupled-plasma reactive-ion etching (RIE). The sulfur hexafluoride/oxygen (SF6/O-2)-based cryogenic process allows etching of nanopillars with an aspect ratio higher than 20:1 and diameters down to 30 nm. Diameters can be further reduced by a well-controllable oxidation process in O-2-ambient and a subsequent etching in hydrofluoric acid. This approach effectively removes surface contaminations induced by former RIE, as shown by x-ray photoelectron spectroscopy. Atomic layer deposition (ALD) is used to establish an all-around Al2O3/Pt stack onto the vertically aligned nanorods. Two approaches are successfully applied to remove the resistant Pt coating from the nanopillar tips.

The direct combination of a photovoltaic system with an energy storage component appears desirable since it produces and stores electrical energy simultaneously, enabling it to compensate power generation fluctuations and supply sufficient energy during low- or non-irradiation periods. A novel concept based on hydrogenated amorphous silicon (a-Si:H) triple-junction solar cells, as for example a-Si:H/a-SiGe:H/a-SiGe:H, and a solar water splitting system integrating a polymer electrolyte membrane (PEM) electrolyser is presented. The thin film layer-by-layer concept allows large-area module fabrication applicable to buildings, and exhibits strong cost-reduction potential as compared to similar concepts. The evaluation shows that it is possible to achieve a sufficient voltage of greater than 1.5 V for effective water splitting with the a-Si based solar cell. Nevertheless, in the case of grid-connection, the actual energy production cost for hydrogen storage by the proposed system is currently too high.

We present a single step and an electrochemical synthesis of vertically aligned ZnO nanorod (NR) arrays, directly on transparent aluminium-doped zinc oxide (AZO) electrodes. The NRs grow from mild, aqueous-based solution at low temperature, with no need for catalysts or additional seed layer. The use of textured AZO as substrate allows for highly effective growth of hexagonally faceted, single-crystalline ZnO NRs along the wurtzite c-axis . The matching of the crystal lattices initiates a self-seeding route, thus the inherent growth habit of the AZO crystallites advances the vertical growth and alignment of NRs. Moreover, the thickness-dependant grain size of the AZO layer provides a valuable feature for tuning the diameter of ZnO NRs grown atop. In the absence of any seed mediator, the interfacial quality is expected to improve significantly. This should enhance the thermal and electrical transport throughout the whole nanostructured transparent electrode. The NR growth was investigated under systematic manipulation of the synthesis variables in order to optimize growth conditions for highly aligned, single-crystalline NRs with a large aspect ratio and a good optical quality. The structure and optical property of the AZO/ZnO NR ensembles were characterized by atomic force microscopy, scanning electron microscopy, X-ray diffraction, photoluminescence, and ultraviolet-visible transmission spectroscopy.

La2O3 grown by atomic layer deposition (ALD) and thermally grown GeO2 are used to establish effective electrical surface passivations on n-type (1 0 0)-Ge substrates for high-k ZrO2 dielectrics, grown by ALD at 250 degrees C substrate temperature. The electrical characterization of MOS capacitors indicates an impact of the Ge-surface passivation on the interfacial trap density and the frequency dependent capacitance in the inversion regime. Lower interface trap densities can be obtained for GeO2 based passivation even though a chemical decomposition of the oxidation states occur during the ALD of ZrO2. As a consequence the formation of a ZrGeOx compound inside the ZrO2 matrix and a decline of the interfacial GeO2 are observed. The La2O3 passivation provides a stable amorphous lanthanum germanate phase at the Ge interface but also traces of Zr germanate are indicated by X-ray-Photoelectron-Spectroscopy and Transmission-Electron-Microscopy. (C) 2011 Elsevier B.V. All rights reserved.

Low leakage ZrO2 dielectrics with a thickness of 7 nm are grown by means of atomic layer deposition (ALD) on GeO2-passivated Ge substrates. Substrate temperatures during the deposition of ZrO2 are set to 150 and 250 degrees C, respectively. The influence of the deposition temperature on electrical and structural properties of metal-oxide-semiconductor capacitors is investigated. A significant impact of the ALD temperature on the high frequency capacitance in inversion is demonstrated. The deposition at 250 degrees C leads to a substantial loss of interfacial GeOx indicated by time-of-flight secondary ion mass spectroscopy. The loss, which gives rise to trap levels near the oxide/Ge interface, shifts the thermal activation energy of minority carrier generation from a full Ge-bandgap energy to midgap energies. (c) 2011 American Vacuum Society. [DOI: 10.1116/1.3521472]

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 1011 eV−1 cm−2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF current ratio greater than 2 × 106 are obtained.

ZrO 2 / GeO 2 dielectrics are grown on germanium substrates by Atomic Layer Deposition (ALD) at substrate temperatures of 150, 200, and 250 °C, respectively. The impact of the deposition temperature on the electrical and structural properties of MOS capacitors is investigated. A significant influence of the ALD temperature on the high frequency capacitance in inversion can be observed, resulting in a shift of the minority carrier response time from 1.15 to 0.2 μs. Time-of-flight secondary ion mass spectroscopy investigations indicate a distinctive depletion of interfacial GeO at higher ALD temperatures, which give rise to trap levels near the oxide/Ge interface.

Dielectric thin films of La 2 O 3 /ZrO 2 deposited by atomic layer deposition (ALD) are investigated to be employed in Ge Schottky barrier p-MOSFETs. La 2 O 3 is used as a thin passivation layer and is capped by atomic-layer-deposited ZrO 2 as a gate dielectric. As the gate contact TiN capped by W is applied, midgap-level trap densities of ~ 3-4 × 10 12 eV -1 cm -2 and subtreshold slopes down to 115-120 mV/dec are achieved. The devices show negative threshold voltages of -0.5 to -0.6 V, as well as peak hole mobility values of ~ 50-75 cm 2 /V · s. Equivalent oxide thickness (EOT) is reduced to 0.96 nm upon postmetallization annealing without degrading the interface properties. The results show the scaling potential of the ALD La 2 O 3 interlayer capped with ZrO 2 gate dielectrics for the integration into sub-1-nm EOT Ge p-MOSFET devices.

The impact of the ZrO2/La2O3 film thickness ratio and the post deposition annealing in the temperature range between 400 °C and 600 °C on the electrical properties of ultrathin ZrO2/La2O3 high-k dielectrics grown by atomic layer deposition on (1 0 0) germanium is investigated. As-deposited stacks have a relative dielectric constant of 24 which is increased to a value of 35 after annealing at 500 °C due to the stabilization of tetragonal/cubic ZrO2 phases. This effect depends on the absolute thickness of ZrO2 within the dielectric stack and is limited due to possible interfacial reactions at the oxide/Ge interface. We show that adequate processing leads to very high-k dielectrics with EOT values below 1 nm, leakage current densities in the range of 0.01 A/cm2, and interface trap densities in the range of 2–5 × 1012 eV−1 cm−2.

The electron Schottky-barrier height (SBH) of platinum germanide diodes on germanium (PtGe/Ge) is tuned by means of incorporation of phosphorous dopants from a spin-on-dopant resist. Thereby a highly doped surface layer on Ge substrates is formed in a rapid thermal diffusion process before the formation of PtGe. Applying a diffusion process of the P atoms at temperatures above 580 degrees C, an ohmic contact behavior is found for the originally Schottky-type barrier diodes and evidence is given for a lowered electron SBH. The contacts exhibit barrier heights to electrons as low as Phi(B,e) = 0.16 eV. In contrast, increased barrier heights for holes of Phi(B,h) = 0.45 eV are found. The results of the electrical characterization are further supported by time of flight secondary-ion mass spectrometry measurements where a pileup of P dopants at the PtGe to Ge interface region is observed. In summary, a damage-free process scheme for the reduction in the electron SBHs in PtGe/Ge diodes is given. The presented approach can pave the way to ohmic-type n-contacts to germanium and is applicable to planar as well as three-dimensional device structures. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3425750] All rights reserved.

We report on the improvement of electrical quality of (100)-Ge/high-k-dielectric interfaces by introducing thin Pt top layers on the dielectric and subsequent oxidative treatments or using a Pt-deposition process with inherent oxidative components. Here, deposition of thin physical vapor deposition-Pt layers, combined with subsequent oxygen treatments, or oxygen assisted atomic layer deposition of Pt on these dielectrics, is applied. Strong reduction of interface trap densities down to mid-1011 eV−1 cm−2 is achieved. The approach is shown for Pt/ZrO2/La2O3/Ge, Pt/ZrO2/GeO2/Ge, and Pt/ZrO2/Ge gate stacks. By x-ray photoelectron spectroscopy evidence is given for oxygen enrichment at Ge/high-k-dielectric interfaces, to be responsible for the improved electrical properties.

We investigate Al2O3- and ZrO2/InAlN/GaN metal-oxide-semiconductor heterostructures (MOS-H) using capacitance-time transients in the temperature range of 25-300 degrees C. A deep-level transient spectroscopy based analysis revealed the maximum interface state density distributions D-it(E) up to 3 x 10(13) and 1 X 10(13) eV(-1) cm(-2) for the Al2O3/InAlN and ZrO2/InAlN interface, respectively. The integral densities of interface states correlate well with the trapping-related gate-lag effect in corresponding InAlN/GaN MOS high electron mobility transistors (HEMTs). This explains the strongly reduced lag effect in ZrO2 MOS HEMTs. We assume hole trapping at oxide/InAlN interface to be a dominant effect responsible for the gate-lag effect in InAlN/GaN MOS HEMTs. (C) 2009 The Japan Society of Applied Physics 10.1143/JJAP.48.090201