In semiconductor wafer manufacturing process, the height of random defects provides an important physical parameter to understand their impact and root cause. In this work, we demonstrate a novel method of defect height estimation based on SEM images without using ground truth or any external reference data of target defect types. Our method is applicable in conditions such as absence of shadows, self-obstruction by defects, lack of precise knowledge of SEM detector geometry and does not require sample tilting or imaging at different working distances, thereby removing major limitations of previous work. The error in our height estimation is $\sim 3$ % compared with $\sim 11$ % for current manual method on same dataset. In addition to improving accuracy and precision, our method reduces the time and manual effort required and can be easily extended to past and new defects for trend monitoring purpose, thus satisfying some key requirements of manufacturing environment.

In chip fabrication, spinner equipment is used for many steps such as creating a uniform layer of photo-resist or etching solvent over wafer. Spinner equipment works by rotating wafer at high speed (∼ 0.1 - 1 kHz) after depositing liquid solvent over wafer. The rotation causes solvent to distribute uniformly over wafer under ideal conditions. Due to impurities and rough terrain (chip layout), the spread is non-uniform. This results in spatially inconsistent chemical processing even though same pattern is printed throughout wafer. Process defects arise due to this non-uniformity. Currently, wafer inspection is done post the spinner process completion. Even though the spinner step is crucial, efficient real time quality tracking and in-line process control methods do not exist. In this paper, we present a novel hardware setup and corresponding software algorithm which makes the spinner track its process and dynamically adjust processing parameters (e.g. speed of rotation, tilt etc.) in order to improve the spread uniformity. We perform theoretical modelling of proposed novel hardware setup and present simulation result to prove its feasibility.

A semiconductor fabrication facility (Fab) manufactures huge volume of wafers and chips. To sustain high production throughput and quality, fast and accurate Fab-In inspection and verification methods are required. These methods intake a lot of spectrum, image and sensor data and enable predicting the quality of a wafer during the Fab-In stage i.e.; roughly 40 days before the final production (Fab-Out stage). It also enables a non-destructive method for quality prediction and thus improves Fab yield. For training such methods, labeled data are required which can be expensive, time-consuming and difficult to obtain in a lot of instances. On the other hand, we have access to vast amounts of unlabeled data that could help us learn patterns of low-quality chips. In this work, we demonstrate that the unlabeled data can be put to good use to improve our prediction of the final quality metrics. We also demonstrate that our approach can accommodate multiple modes of data unlike most existing systems. The system is completely configurable and the final models are completely "safe" in the sense that we always ensure accuracy better than or equal to that possible with normal labeled data. We showed results over one in-house data and one open source data for reproducibility.

Material spectroscopy (MS) is used to identify elemental composition of micro particles. Energy dispersive X-Ray spectroscopy (EDX or EDS) is one such method. EDX analysis of defects found during wafer inspection aids in performing their root cause analysis (RCA). However, due to large processing time of EDX, it is applied very judiciously on a few chosen defects only. A wafer can typically contain ~100s of defects. The defect coverage of EDX is ~1% [1] thereby resulting in considerable gap in proper diagnosis and RCA. To overcome this issue, we demonstrate a soft method to perform MS of defects. The method predicts accurate elemental compositions of defect and background (~80%F1) when compared with EDX predictions on the same defect. The method is fast and could increase defect coverage for MS to ~100%• This can significantly improve RCA and thus help in Yield Enhancement (YE). Computing exact YE is complex as it involves many hidden and un-trackable factors. We perform theoretical high level modelling of more tangible factors i.e. profitability per month of Fab which is directly proportional to YE and theoretically show 14.6% improvement using our soft MS method.

INTRODUCTION: MURA defects in LED/LCD panels are one of the most challenging defects for Automatic Defect Classification and Localization (ADC) due to their extremely low contrast when compared with the background. Manual detection is subjective, error prone, very tedious and time consuming. Even when the type of MURA defects can be ascertained manually, the exact bounding box for defect is hard to determine. Various heuristic based image processingtechniques have been applied giving sub-optimal accuracy over generic datasets.OBJECTIVES: The primary objective of this paper is to check whether the state of the art DL (Deep Learning) network for general object classification and localization (MSCOCO PASCAL VOC etc.) can be applied successfully for MURA Defect Classification and Localization.METHODS: In this paper we present a single DL pipeline for classification and localization which for the first time is applied for MURA defects. Naive DL network - Single Shot multi-box Detector (SSD, pre-trained on ImageNet) was not sufficient to give a good F1 score because of the nature of the defect. Accuracy improved a little after applying various DLspecific optimization methods such as loss function optimization, network optimization etc. Utilizing the knowledge from MURA domain for data augmentation, like filtering based on image capture wavelength etc. improved the results significantly.RESULTS: Using optimization techniques that are from both DL domain as well as specific to MURA domain, we show improvement in the accuracy of the base DL pipeline from ~30% to ~80%. Minimum heuristics were used to define the pipeline so that it can easily adapt to any new MURA dataset. The paper shows the importance of domain specific preprocessing steps for the designed network in case of MURA defects.CONCLUSION: Using DL, MURA classification and localization had not been tried before. For the first time we demonstrated results for both classification and localization of MURA defects using state-of-the-art DL network with F1~80%. We also conclude that state-of-the-art network for general object detection can be reused with the help of Transfer Learning (TL) concept and fine-tuned with MURA domain specific optimizations mentioned in paper for optimalperformances in MURA domain.

A typical scene under the camera lens of a wafer inspection equipment consists of device features that are at different height relative to each other. To image such a scene, conventional camera systems within the equipment apply a single focus setting to all the features in the field of view. The resulting images consist of blurred regions corresponding to features that are not located at the object distance conforming to the lens focus setting. Such defocused images reduce the accuracy of defect detection process and adversely affect wafer yield. In this paper, we present a method to overcome this limitation using spatial light modulator (SLM). By optimizing the voltage to the cells of SLM, it can be converted into an array of partitioned thin lenses. Using this unique property of the SLM, we describe a process for obtaining "all-in-focus", high resolution image of the entire field of view. Our simulation results show clearly the benefit of our solution.

The status and progress of InP photonic integration is reviewed. Infinera has previously reported on the manufacturing of 100 Gb/s InP-based large-scale photonic integrated circuits. These PICs, based on amplitude modulation and with more than 50 discrete functions per chip, have now reached a high level of manufacturing maturity, and have furthermore redefined reliability standards for InP components, having achieved more than 900 million field hours without a single failure as of this writing. In this paper, we will describe manufacturing status for the 3rd generation of Infinera’s LS-PICs, which feature 500 Gb/s capacity using phase modulation on the transmitter chip, and coherent detection on the receiver chip, and which now form the heart of Infinera’s 500G DTN-X transport system, released in mid-2012. These new PICs have an order-of-magnitude increase in chip complexity, and a commensurate increase in fabrication complexity from III-V epitaxy through wafer fab, die fab, and test. The architecture and performance of Infinera’s PICs will be described, along with relevant yield and production metrics that demonstrate this platform is at once manufacturable and scalable.

In this talk, we describe the monolithic integration of 10 InP-based phase-modulated transmitter channels employing polarization multiplexing and quadrature phase-shift keying coherent modulation format to provide an aggregate 500Gb/s bandwidth on a single chip.

In this paper, the current state of the art for large-scale InP photonic integrated circuits (PICs) is reviewed with a focus on the devices and technologies that are driving the commercial scaling of highly integrated devices. Specifically, the performance, reliability, and manufacturability of commercial 100-Gb/s dense wavelength-division-multiplexed transmitter and receiver PICs are reviewed as well as next- and future-generation devices (500 Gb/s and beyond). The large-scale PIC enables significant reductions in cost, packaging complexity, size, fiber coupling, and power consumption which have enabled benefits at the component and system level.

InP photonic integrated circuits (PICs) for advanced modulation format transmission, which enable high spectral efficiency, reduced complexity, high reliability, and low power consumption, will be reviewed.

We report the first demonstration of a large-scale InP-based transmitter photonic integrated circuit (PIC) capable of 10-channel x 40 Gb/s per wavelength polarization-multiplexed RZ-DQPSK modulation. (C) 2008 Optical Society of America

We demonstrate 100-Gbps tunable transmitter (Tx) and receiver (Rx) photonic integrated circuits (PICs) with minimal performance penalties over a 150 GHz tuning range.

We have successfully demonstrated large-scale photonic integrated circuit (LS-PIC) transmitters with monolithically integrated semiconductor optical amplifiers. Data is presented for for 10 channel devices operating at 10 and 40 Gb/sec.

We demonstrate an InP-based monolithically integrated reconfigurable optical add-drop multiplexer consisting of an array waveguide grating, a semiconductor optical amplifier, four 2x2 Mach-Zehnder optical switches, and four PIN photodetectors using the asymmetric twin waveguide technology. The total chip size is 10 x 6 mm, and each of the components in the circuit exhibited performance similar to that achieved in a discrete form. The add-drop functionality of the chip is demonstrated via the routing of the signal from the add port to the drop/output port.

We investigate high linear response tapered photodiodes composed of bulk and multiquantum-well absorption layers based on the integratable asymmetric twin waveguide architecture. The tapered shape reduces space-charge induced nonlinearities, enhancing the saturation current densities at high input optical powers. The 1-dB compression current density for an InGaAsP bulk active layer photodiode (BPD) is in excess of (2.8 plusmn 0.3) kA/cm2, compared to quantum-well photo- diodes (QWPD) in the same materials system that saturate at (1.2 plusmn 0.1) kA/cm2. We find that the limited density of states of QWPDs leads to the early onset of current saturation. The BPD has a polarization sensitivity of SPol = (1.0 plusmn 0.5) dB and responsivity R = (0.3plusmn0.03) A/W at a wavelength of 1.55 mum, whereas the QWPD has SPol = (7plusmn1) dB and R = (0.55plusmn0.05) A/W, while both have a bandwidth of (11 plusmn 1) GHz.

An InP-based monolithically integrated optical add-drop multiplexer (ROADM) is demonstrated with the asymmetric twin waveguide (ATG) technology. Its add/drop functionality has been measured and shows > 20 dB drop extinction ratio.

A monolithic integrated optical receiver is demonstrated by using the asymmetric twinwaveguide (ATG) technology. This device shows a peak responsivity of 8±0.2 A/W, and a 3dB optical bandwidth of 10±1 GHz, equivalent to a 265 GHz gain-bandwidth product.

We demonstrate an integratable, high linearity (>15 dBm optical power), high bandwidth ((11plusmn1) GHz), polarization insensitive tapered photodetector with a peak responsivity of (0.25plusmn0.03)A/W. The tapered photodiode of this work consists of a lower passive guide for enhanced fiber coupling, with the active absorption region grown on the waveguide surface.