Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si $_{\text{0.75}}$ Ge $_{\text{0.25}}$ etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.

We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. SD epi patterning at 30nm vertical N-P space and high-aspect-ratio SD contact formation are successfully demonstrated. Functional devices with excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) are reported for bottom and top devices, for both N- and PMOS. Middle dielectric isolation (MDI) formed by SiGe replacement processing is introduced as an enabler for monolithic CFET inner spacer formation and multi-Vt patterning.

Buried power rail (BPR), a novel integration approach for further device scaling, brings in new patterning needs and requirements, the most importantly, the challenging middle-of-line (MOL) patterning process steps. In this paper, some of the critical plasma dry etch development processing results for the FinFET device flow with BPR integrated are presented. Mainly, the study was focused on plasma dry etch development of high aspect ratio Via contact to BPR metal (VBPR) and Trench contact etch (M0A) to the source/drain (S/D) device region. We demonstrate the short-free M0A (no attack on the neighboring gates) contact etch to the S/D, with the high etch selectivity values obtained in case of the dielectric SiO2 trench etch to the thin Si3N4 liner (deposited over epitaxial S/D), and subsequently the high selectivity values during SiN liner etch to the underlying S/D (SiN liner etch results in 0nm epitaxial film loss). Patterning of high aspect ratio (HAR) Via consisting of the multi-stack, SiO2/SiN/SiO2/SiN dielectric, landing on the bottom BPR metal was achieved, with the target critical dimension (CD) required to avoid shorting to the adjacent gates. Additionally, we report our learnings on how choice of buried power metal (W, Ru and Mo) impacts the etch requirements, i.e., the etch challenges associated by using Ru and Mo as a replacement for standardly used W metal.

As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also contacting directly the device’s S/D-epi. As for gate wiring, to enable in this work its access from both wafer sides, gate is also connected to BPR via V0 landing on it and on a neighboring M0A line set only on field-oxide. A single-step metallization for M0A and VBPR is preceded by in situ preclean(s) optimized for improved BPR-VBPR contact interface and ${R}_{\text {ext}}$ , as confirmed electrically and by physical analysis. After FS processing, wafer flipping, bonding, and extreme thinning, highly scaled, ~323 nm deep nano-through-Si-vias (nTSVs) land on BPR, with tight overlay control and unchanged BPR resistance [26%–29% lower with improved tungsten (W)-fill], connecting them to the first backside (BS) metal level (BSM1). By moving the power delivery network to the BS (BSPDN), besides alleviating FS routing congestion, considerably smaller dynamic and static IR drop values are predicted from on- chip power heat maps generated for a low power 64-bit CPU at 2-nm design rules: 82% and 96% less worst-case values versus a reference configuration, respectively. P/NMOS show similar or even superior ${I}_{ \mathrm{\scriptscriptstyle ON}}$ – ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ after BS processing and extra anneal(s) added for ${V}_{T}$ recovery, mobility and bias temperature instability (BTI) improvement—up to 8%/15% higher ${I}_{ \mathrm{\scriptscriptstyle ON}}$ linked to anneal selection.

This work reports metal exploration for buried power rail (BPR) and Via-to-BPR (VBPR) towards the 1 nm node. For tungsten, which is the first choice of BPR metal at the 3 nm node, we optimize W metallization stack to minimize line resistivity, together with ways to reduce W-BPR - W-VBPR contact resistance (R). For scaled BPR CDs at the 2 nm and 1 nm nodes, we introduce molybdenum at the BPR level and benchmark its R and electromigration against W and Ru metallization. Additionally, Mo dry & wet, selective etch processes to enable Mo-BPR recess in fin/STI stack at fin pitch 24 nm, and a Mo wet clean process for VBPR contact formation are also demonstrated.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, BPR plug barrier, and fin reveal are optimized to enable BPR scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. Ru-BPR meets BPR line R target <; 50 Ω/μm at ~2× smaller aspect ratio than W-BPR thanks to its lower resistivity and thinner TiN liner. A good VBPR pre-clean prior to TiN liner & Ru deposition with W-BPR underneath, is found to be crucial to achieve low Ru-VBPR resistance. Calibrated TCAD simulations show Ru-VBPR with thin TiN liner meets VBPR R target <; 75 Ω. W-BPR interface with Ru-VBPR shows robust electromigration for >1100 h at 5 MA/cm 2 at 330 °C.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

In 5 nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24 nm. Fin depopulation is mandatory to enable the area scaling, but it becomes challenging at small pitches. In the first part, each process flow is simulated in order to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and process non-idealities are characterized in a second part and used to calibrate the 3D model. In the third part, a process sensitivity analysis is conducted to compare the impact of overlay and CD variations on various options.