This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.

Nanosheet device is being introduced in the industry as post-FinFET CMOS device architecture thanks to its wider transistor effective width/footprint by stacked nanosheet channels. Nanosheet device scaling will continue by combining slow pitch/track scaling and device architecture evolutions, such as Forksheet and CFET. Backside power delivery combined with nanosheet device architectures is expected to provide smaller IR drop and better scalability. It can be extended to functional backside, which contains variety of components at backside for further system-on-chip scaling/performance improvement.

Using an advanced Design Technology Co-Optimization (DTCO) framework, we benchmark gate-all-around Nanosheet (GAA-NS) and Forksheet (FS) architectures at multiple metal pitches (Mx), active widths ($\mathrm{W}_{\mathrm{Ns}}$), and contacting schemes, viz. buried power rail (BPR) and backside power rail (BS-PR) with backside contact (BSC). Interestingly, we find that while at larger cell height (CH), FS perform better than NS, at smaller CH it is the reverse. From a performance perspective, while BSC does not provide any benefit for a wrapped-around contact baseline, it does provide an active width advantage (2 nm extra $\mathrm{W}_{\mathrm{NS}}$). We also introduce a novel GAA-FS device for enhanced gate control and investigate asymmetric-FS for optimized performance at different Mx.

Using an advanced design technology co-optimization (DTCO) framework, we investigate multi-threshold (multi-$V_{\mathrm{T}})$ options in gate-all-around nanosheet (GAA-NS) FETs at ultra-scaled vertical pitch. This is achieved by allowing inner-gate work-function to be pinned due to very thin metal layers, while only modulating outer-gate work-function. It is shown, that while inner-outer work-function mismatch does result in on-current degradation, the impact is not significant within the mismatch range required (±300 meV) to achieve $3-V_{\mathrm{T}}$ device options. Thus, we propose a path for vertical pitch scaling whereby, higher stacked NS can be processed with relative ease in addition to enhanced performance.

In sub 10 nm nodes, the growing dominance of interconnects in chips poses challenges in designing large-size static random-access memory (SRAM) subarrays. The main issue is the write failure problem arising from the increased resistance and capacitance for bitline (BL) and wordline (WL). To tackle this issue, the SRAM subarray design incorporates conventional (Conv.) divided WL and divided BL techniques based on 14-& Aring;-compatible (A14) nanosheet (NS) technology. This approach allows for various subarray sizes with successful write operations, resulting in improved subarray-level performance and power (PP). However, the additional logic gates come with an area penalty that may degrade the overall performance, power, and area (PPA) at the macro level due to increased inter-subarray interconnect overhead. To overcome this limitation, the active interconnect (AIC) design is proposed with the features of fabricating another or multiple active regions at the back-end of line (BEOL) layers. By moving these extra logic gates from front-end of line to BEOL in the AIC divided subarray design, the area penalty is significantly mitigated without compromising PP compared to the standard (Std.) and Conv. divided counterparts. To achieve this concept, carbon nanotube gate-all-around transistor is explored as potential BEOL-compatible device. In this research, a comprehensive design-technology co-optimization analysis is conducted to verify the value and potential benefits of up to 65% macro-level energy-delay-area product improvement by AIC divided subarray design compared to the Std. subarray design.

The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.

This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

Complementary field-effect transistor (CFET) has successfully boosted the area scaling of static random access memory (SRAM) bitcell due to its stacked architecture. However, this architecture introduces taller via connection from the frontside back-end-of-line (BEOL) signals to the bottom pass-gate devices, resulting in increased bitline (BL) and wordline (WL) capacitances ( ${C}_{\text {BL}}$ and ${C}_{\text {WL}}$ ) compared to nonstacked SRAMs. Previous research has reported that the higher parasitic capacitance hinders the power and performance gains between nodes. In this work, as a hypothetical device option aside from sequential and monolithic CFET, hybrid CFET is introduced in SRAM design with the features of double-sided interconnect design in 3-Å-compatible technology (A3). To assess its potential value in future SRAM roadmap, a comprehensive design technology co-optimization (DTCO) “what-if analysis” has been conducted. Hybrid CFET enables relaxation of metal width and shorter via connections in SRAM design compared to previous approaches. Therefore, A3 hybrid CFET SRAM can provide up to 41%, 25%, 35%, 32%, and 45 mV improvements of ${R}_{\text {WL}}$ , ${C}_{\text {BL}}$ , ${C}_{\text {WL}}$ , read speed, and write margin, respectively, compared to sequential and monolithic counterparts. Moreover, it also exhibits 77% energy–delay–area product enhancement compared to 14-Å-compatible nanosheet technology at the macro level (128-MB cache). These compelling results motivate further research and development of the process flow for hybrid CFET devices in SRAM technology in the future.

Fin depopulation, thinner and taller fins, and the step towards Nanosheet technologies has been helping in maintaining the rhythm of the semiconductor technology roadmap. Nevertheless, further area scaling causes a drastic reduction in active width as well as a challenging routability. On this regard, the Complementary-FET is a strong contender as device for next generation technologies. The stack of p- on n-FETs offers several opportunities for device scaling and optimization. However, it also poses several challenges that need to be carefully analyzed in a design-technology cooptimization framework.

This paper evaluates Power-Performance-Area (PPA) tradeoffs and integration challenges of three types of backside power connections: Through Silicon Via in the Middle Of Line (TSVM), Self-Aligned Front-to-Back via (BPR) and Backside contact (BSC) for nanosheets at N2 and A14 nodes. From TSVM to BPR to BSC, solid PPA gain s are shown for High Density Logic, at the expense of increased process complexity. While TSVM remains competitive in N27-Track high-performance technology, BSC shows maximal gain s in A145-Track high density node.

Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Å-compatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions.

In this work, the impact of metal hybrid height (H^2) and airgap (AG) scaling boosters are evaluated based on an enhanced Ring Oscillator (RO) framework that accounts for Place and Route (PnR) aspects of the back end of line (BEOL) interconnects. When targeting best performance, extended AG with high aspect ratio (AR) lines appears to be the optimal choice as it allows reducing both capacitance (C) and resistance (R). Combining AG with H^2 provides minimum C at an increased R making it more suitable for power optimization.

In this paper, backside power delivery network (BS-PDN) and a high density 2.5D Mimcap (Metal-insulator-metal capacitor) are applied to improve dynamic IR-drop of 2D and 3D ICs at a sub-2nm node. An on-chip PDN design and IR drop modelling framework is proposed and calibrated with the physical design results of 64-bit low power CPU. The calibrated framework is applied to 2D IC PDN with various Mimcap integration and then to 3D IC PDN. The 2.5D Mimcap used here was manufactured with optimized capacitance density of ~70 fF/um 2 . The BSPDN using 2.5D Mimcap has 32.1%/23.5% improvement in IR drop over the no Mimcap/2D Mimcap counterparts respectively, and BSPDN shows 36.3% improvement over the front side PDN (FSPDN) counterpart. Furthermore, by using 2.5D Mimcap + BSPDN in the 3D-IC, the top logic die IR drop is improved by 21.7%.

We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.

The metal resistance increase due to interconnect pitch scaling was traditionally offset by interconnect length scaling. This is no longer the case for deeply scaled nodes with narrow critical dimensions (CDs) of metals. Static random access memories (SRAMs) route long critical signals such as bitlines and wordlines in lower metal layers of the back-end-of-line (BEOL) and are particularly affected by this metal resistance increase. Buried power rail (BPR) has been proposed in sub-5-nm nodes for routing power and ground lines to improve the performance and density of standard cells and mitigate voltage IR drop issues. We extend the work by exploring the use of buried interconnect for both signal and power routing in SRAMs with minimal process flow changes to the already proposed BPR technology. A high-accuracy 3-D field solver is used for accurate parasitic extraction of SRAM bitcells with buried interconnects. Industry-standard methods are used to evaluate the SRAM macro-level power–performance metrics. We show that the buried interconnects can improve SRAM access time by up to 11%, write time by up to 28%, and dynamic power by 4%, effectively equivalent to one full technology-node gain improvement.

Continuous CMOS scaling enabled by complex transistor topology raises self-heating concerns. Here, we perform a comparative thermal benchmarking of architectures for current and projected device technologies: finFET (iN8–iN5), nanosheet (iN5/iN3), forksheet (iN3) and monolithic CFET (iN2) using an in-house Monte Carlo framework with first-principles heat carrier properties. Experimental validations highlight the impact of non-diffusive thermal transport inside logic cells. Thermal resistance oscillates node by node but grows near linearly with power density. Channel fragmentation (finFET to nanosheet) raises temperatures, while buried power rails help reduce self-heating. Excess channel heating (relative to the cell boundary) of 0.8–1.6 and 10–19 degrees is observed for baseline (0.7VDD at 2GHz clock) and turbo (1.4VDD at 6GHz clock) operation scenarios respectively.

SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM.

We present a new extended scale length theory targeting low-dimensional FETs and derive a new Carbon Nanotube FET (CNFET) leakage compact model which also includes inelastic band-to-band tunneling. We accurately predict CNFET minimum drain leakage (spanning 10 10 range) within 3x vs. experimentally calibrated Non-Equilibrium Green Function (NEGF) simulations (10 5x error without our model). Our extensive design-technology co-optimization (DTCO) quantifies, for the first time, large Energy Delay Product (EDP) benefits (up to 4.8x - 7x depending on the reference) of CNFET ring oscillators (vs. silicon NanoSheet, silicon ForkSheet, silicon CFET) at the 2nm node.