As logic scaling enters the angstrom era, vertically stacked complementary field-effect transistors (CFETs) based on atomically thin two-dimensional (2D) semiconductors offer a potential route to extend device scaling beyond the A2 node. Here, we develop an A2-oriented 2D CFET integration flow with a CPP of 36 nm and Lg of 10 nm and present initial demonstrations of several key process modules. Despite their atomically thin channels, 2D GAA CFETs do not provide a contacted poly pitch scaling advantage over Si GAA CFETs at the A2 node, because contact formation constraints impose a similar minimum CPP of 36 nm. We also combine a critical assessment with a multiscale power-performance-area (PPA) evaluation framework spanning quantum transport simulations, compact-model generation, A2-targeted 2D CFET gate-all-around (GAA) integration-flow definition, parasitic extraction and circuit-level benchmarking. Our analysis, however, shows that the expected benefits of 2D GAA CFETs are strongly constrained by non-idealities, in particular high contact resistance and dominant layout-induced parasitic capacitances. Although architectural optimization can improve the Ieff/Ceff ratio, the associated rise in absolute capacitance limits circuit-level gains. Meaningful progress will require co-optimization of contacts, transport and parasitics, together with 2D-specific CFET architectures.

This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.

This study investigates the overlay performance of a 2-level Ru semi-damascene integration using a Spacer-is-Dielectric (SID) SADP strategy to create 18 nm metal pitch Ru metal lines combined with fully self-aligned vias (FSAV). Furthermore, the impact of via overlay on FSAV electrical performance was experimentally assessed. Results show that <= 3 nm lot M(x)block-to-M-x overlay residuals can be achieved using an SID-SADP approach with TiN as hard mask. Moreover, an >80% kelvin via yield could be obtained for a via y-overlay range of 10 nm and via x-overlay range of 11 nm, highlighting the FSAV process's robustness for future interconnect scaling.

This work reports variable metal width Ru semi-damascene bottom metal line integration at metal pitch (MP)=18-26 nm, for the first time at high-aspect ratios of 4 and 6. It is also the first report on routing of such lines to a top semi-damascene metal level using a fully self-aligned via (FSAV). Average core-gap line resistance (R) at MP=18 nm is similar to 240 Omega/mu m at AR6. Line-line leakage yields of 50% and 30% at AR4 and AR6, respectively, is achieved at MP=18 nm which exceed 90% and 70% at MP=20 nm. MP=18 nm, AR4 line-line TDDB at 100 degrees C show an extrapolated failure time of >10y. Ru FSAV fabricated on AR4, MP=18 nm Ru line has a kelvin resistance of similar to 20 Omega at via bottom CD similar to 9.4 nm and via height similar to 8.4 nm. Electromigration (EM) on single vias show robust Ru-Ru interface with no failures post 135h of EM stress at similar to 10 MA/cm(2) and 330 degrees C.

This work presents a novel Spacer-is-Dielectric (SID) SADP Ru semi-damascene integration scheme by using metal-based core and gap hard masks. More than 70% yield in tested line resistance and line-to-line leakage, especially in MP18 structures, confirm the flow feasibility. The tested MP18 structures show a median line resistance of, low line-to-line leakage at 1V, and breakdown voltages in the range of 12-14V.

The electronic transport properties of atomic-layer-deposited Ru thin films and nanowires were investigated in the temperature range between 0.1 and 30 K by means of magnetoresistance measurements. The nonlinear behavior of the longitudinal and Hall resistivities was used to extract information on carrier densities and mobilities. The analysis revealed that for thin films, holes exhibit lower mobility but have a much greater concentration than that of electrons, in contrast to bulk at room temperature where the electron and hole densities are expected to be equal, with holes having a larger mobility. For Ru nanowires, the saturation of magnetoresistance suggests a vanishing electron concentration possibly due to excess carrier concentration at the edge causing increased recombination supported by defects. For Ru thin films, weak antilocalization effects provided insight into phase coherence and spin-orbit scattering lengths, indicating that electron-phonon interactions are the dominant scattering mechanism.

Airgap integration in 18 to 26 nm metal pitch (MP) two-metal level semi-damascene interconnects with fully self-aligned vias (FSAV) on 300 mm wafers is reported. The first metal layer (Mx) is patterned using EUV-SADP with subsequent direct metal etch of the Ru film. Airgap is integrated at a targeted height of 4-6 nm below the top metal lines allowing for FSAV compatibility. 80% of kelvin vias landing on Mx at MP18 meet the < 50 ohm resistance target specification and 40% of them meet the via-to-line leakage target of <100 pA. The airgap line-to-line capacitance is found to be 40% lower compared to the dielectric gap fill reference.

This study highlights the effectiveness of a novel two-metal-level semi-damascene integration approach using fully self-aligned pillar-vias (FSAV) for interconnects ranging from 18 to 26 nm metal pitch. We employ EUV-SADP-SIM patterning scheme and direct metal etch of Ru to demonstrate the proof of concept on 300 mm wafers. This integration gives lower via resistance than the previously reported schemes and promises lower capacitance. Furthermore, it significantly widens the via litho and etch process window, making it more attractive for advanced semiconductor manufacturing.

This work provides keys for optimizing nanosheet-based monolithic Complementary Field-Effect Transistors below 50nm gate pitch, relevant to industry “sub-nm” nodes. The impact of Source/Drain epitaxial growth, trench contact size, junction design and gate pitch on device performance are reviewed for top and bottom devices demonstrating electrically functional 42nm gate pitch devices. TCAD, calibrated to target DUT’s, depicts up to 50% performance boost at low contact resistivity and high S/D doping, paving the way for next-generation CFET devices.

A novel metal stack scheme with a sub-nm, sandwiched TiN or W layer, a so-called defect mitigation layer (DML) between Ru is proposed and found to be less prone to lateral attack and line-break formation during direct-metal-etch (DME) of Ru semi-damascene (semi-D) lines compared to those without DML. With increasing thickness (t k ) of TiN-DML, we achieve up to 5x lower defect density and resistance (R) yield >99%, <5% 1 σ of R on AR~4-6, CD~6-11 nm, metal pitch (MP)=18-26 nm lines. The improvement is higher on AR~6 lines than AR~4 which makes DML a promising approach to enable AR≥6 semi-D interconnects. No R penalty is found with TiN-DML for the investigated line lengths> 10 μm. Thermal shock reliability test shows good quality of HAR Ru line interfaces with TiN-DML.

High-aspect ratio (HAR-6-8) bottom Ru metal lines (M2), at CDs 7-10 nm and metal pitch (MP) 18-26 nm, in a two-metal level Ru semi-damascene interconnect configuration with fully self-aligned via (FSAV) is reported for the first time. M2 is patterned using EUV-SADP and subsequent direct-metal-etch (DME) of Ru film. At critical dimension (CD) of 10 nm, the resistance (R) of Ru line at AR6, measures at 235 Ω/μm which is 75% lower than the simulated Cu line R at AR2. The R yield of Ru lines across 300 mm wafer is >90% for MP20-26 nm. The FSAV R is competitive; vias landing on AR6 lines show a median R~33Ω with bottom CD of 8.5x12.3 nm 2 . Good quality of HAR Ru line interfaces is indicated by thermal shock tests showing no change in line R post 1000 h of thermal cycling between -50°C to 125°C.

Nb x Ti (1-x) N is a promising alternative to replace conventional Nb in superconducting devices. In this work, short loop devices with metal lines and vias were fabricated in IMEC 300-mm pilot line using direct metal etch, semi-damascene approach. Single line resistance of Nb x Ti (1-x) N wires show that >95% of devices meet the expected resistance of <5000 Ω/μm and leakage measurements show that >95% of devices have low leakage of <1E–16 A/ μm. Low temperature measurements show that the Nb x Ti (1-x) N wires have transition temperature of 12.5K within 0.5K that of thin film and a critical current of 0.15 mA, within 2X of theoretical maximum.

3D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL architectures, such as backside power delivery network (BSPDN) or Vertical-Horizontal-Vertical routing style, are required to connect 3D stacked devices without wiring congestions and resistance increase. Process/material innovations are necessary to enable high aspect ratio and 3D integration in CFET integration with new MOL architectures.

We present the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects varying 26 to 18nm metal pitch, using an EUV-based SADP scheme and subsequent direct etch of Ru, manufactured on 300mm wafers. The integration flow uses the subtractive etching principle of Ru on two subsequent metal levels. Single via resistance landing on 18nm pitch Ru lines shows that > 85% of the devices meet the target of <50Ω. Furthermore, the via chain offers a yield of 60% with a resistance close to the target of ~5k Ω. Besides, we show good uniformity and high VBD via-to-line with MP20 to MP26, establishing FSAV.

Buried power rail (BPR), a novel integration approach for further device scaling, brings in new patterning needs and requirements, the most importantly, the challenging middle-of-line (MOL) patterning process steps. In this paper, some of the critical plasma dry etch development processing results for the FinFET device flow with BPR integrated are presented. Mainly, the study was focused on plasma dry etch development of high aspect ratio Via contact to BPR metal (VBPR) and Trench contact etch (M0A) to the source/drain (S/D) device region. We demonstrate the short-free M0A (no attack on the neighboring gates) contact etch to the S/D, with the high etch selectivity values obtained in case of the dielectric SiO2 trench etch to the thin Si3N4 liner (deposited over epitaxial S/D), and subsequently the high selectivity values during SiN liner etch to the underlying S/D (SiN liner etch results in 0nm epitaxial film loss). Patterning of high aspect ratio (HAR) Via consisting of the multi-stack, SiO2/SiN/SiO2/SiN dielectric, landing on the bottom BPR metal was achieved, with the target critical dimension (CD) required to avoid shorting to the adjacent gates. Additionally, we report our learnings on how choice of buried power metal (W, Ru and Mo) impacts the etch requirements, i.e., the etch challenges associated by using Ru and Mo as a replacement for standardly used W metal.

This work reports for the first time, a middle-of-line (MOL) compatible, barrier/liner-less ALD molybdenum (Mo) process on SiO 2 used for Via-to-buried-power-rail (VBPR) and contact-to-active (M0A) dual-damascene metallization. We also compare the MOL-compatible ALD process with the front-end-of-line (FEOL)-compatible ALD process used for BPR fill as reported in [1]. In addition, we report that Mo-BPR can withstand 800 °C anneal, demonstrating its compatibility with high thermal budgets of FEOL. Furthermore, we demonstrate for the first time, integrated (i.e. w/o air-break) precleans prior to Mo-VBPR deposition for contact formation with Mo-BPR. The precleans remove MoO x from Mo-BPR surface proven by SIMS characterization at blanket film level. The effectiveness of precleans is further proven at via level with a good agreement between measured and predicted Mo-VBPR resistance (R) landing on Mo-BPR. Finally, the first downstream electromigration tests on Mo-BPR annealed at 800 °C, show no failures for >150 h at 5 MA/cm 2 & 330 °C proving its robust behavior.

We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.