This work reports on demonstration of monolithic complementary field effect (CFET) transistors using direct backside (BS) contact (DBC) to source and drain (SD) of the bottom PMOS device. We compare two integration options to avoid shorts between DBC and gate and/or Si substrate relying either on the use of an offset spacer or on the formation of a bottom dielectric isolation from the backside (BS-BDI). We show that a DBC layer registration accuracy of < 3 nm can be achieved with high order correction modelling which can be transferred to consecutively processed BS layers. Both integration options result in functional bottom (pFET) and top (nFET) CMOS devices on a common gate at 60 nm gate pitch. While the BS-BDI option requires additional process steps, it results into parasitic transistor leakage suppression due to replacement of the Si substrate under the gate by dielectric. Moreover, it provides better tolerance to DBC misplacement and enables maximizing contacting area.

This work reports on the first demonstration of monolithic CFET CMOS co-integrating Middle Dielectric Isolation (MDI), Inner Spacers (ISP) and Stacked frontside patterned Contacts. The flow results in functional CMOS devices on a common gate architecture. The MDI formation is done before source drain (SD) recess for optimal bottom junction (BJ) formation. The paper discusses the challenges of using stacked contacts to form the top device junction (TJ). Finite accuracy of bottom device contact (BC) registration from frontside results in a limited process latitude to access the top device channel for TJ formation while keeping the integrity of MDI and ISP. Top device survival rate increases from 11% to 79% by eliminating the frontside BC. We show feasibility of moving BC to the wafer backside with registration accuracy below 3nm.

Complementary FET (CFET) is a device where n-and p-MOS transistors are stacked. In consequence, the source and drain metal contacts also need to be stacked. In this work, we investigate the high aspect-ratio (AR) patterning and metallization required for the formation of metal contacts in the monolithic CFET integration. The bottom contact is processed first by patterning deep trenches in between gates with AR > 13, CD = 17 nm and with a pitch of 60 nm. Subsequently, these high AR trenches are metalized, polished, and etched back. Afterwards, proper dielectric isolation needs to be in place before building the top contact. Finally, routing vias and the first BEOL layer are implemented all through the front side of the wafer for electrical tests.

As further scaling of standard cells (SC) continues, new innovative techniques are required to the keep pursuing Moore’s law. Middle-of-line (MOL) scaling boosters are one of the most critical modules to scale standard cells. In this work, we present new morphological and first-time electrical data of 8 nm self-aligned tip-to-tip (T2T) of MOL metal layer as a cell boundary to enable Vertical-Horizontal-Vertical (VHV) cell architecture. This will be the key feature to further downscale standard cell height from 5 to 4 tracks. A VintB space of 8.3 nm with standard deviation of 1.6 nm was achieved. For the M0B, a T2T of 5.9 nm with a standard deviation of 1.6 nm was achieved. Electrically a M0B T2T leakage of <1e–10A/m was obtained on 14% of the measured sites for 8 nm T2T, 30% for 10 nm T2T and 40% for 12 nm T2T.

Complementary FET (CFET) is a device architecture where n-and p-MOS transistors are stacked. As a result, the source and drain contact metals also need to be stacked. In this work, we tackle the high aspect-ratio (AR) patterning and metallization required for the monolithic CFET integration scheme. The bottom contact is formed by filling trenches with W up to AR =16 and CD =12 nm, followed by CMP and metal etch back at 45, 50 and 60 nm pitch printed by EUV lithography. We study the accuracy of the metal EB process using scatterometry, TEM and a new CDSEM technique, and observed a global Vertical Edge Placement Error (VEPE) as small as 2% for etch amounts ranging from 60 to 100 nm. Excellent correlation with electrical data was obtained. The top contact is separated from the bottom contact by an oxide fabricated in similar way (deposition, CMP and EB).

We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. SD epi patterning at 30nm vertical N-P space and high-aspect-ratio SD contact formation are successfully demonstrated. Functional devices with excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) are reported for bottom and top devices, for both N- and PMOS. Middle dielectric isolation (MDI) formed by SiGe replacement processing is introduced as an enabler for monolithic CFET inner spacer formation and multi-Vt patterning.

A new cell routing architecture called vertical-horizontal-vertical (VHV) which requires a two-level (2L) middle-of-line (MOL) scheme has been proposed as a scaling booster to enable 4-track (4T) standard cell (SDC) templates for beyond the 2 nm technology node. In this work, we demonstrate an innovative integration strategy using the semi-damascene technique to implement the 4T VHV, enabling the precise definition of a tight boundary between SDC’s which requires two vias with zero-line extension facing each other and a tip-to-tip (T2T) at the underlaying layer, all at a distance of ’one CD’ of the top layer. As a result, we obtained an average via CD=10.5 nm with a resistance of $24 \Omega$, and a T2T =8.9 nm. Both vias and T2T were self-aligned to the 18 nm pitch layer above.

As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.

We report on forksheet field-effect transistors that are isolated from the substrate by bottom dielectric isolation (BDI) formed by replacing a SiGe epitaxial layer with a dielectric film while the devices are anchored to the substrate by forksheet walls. Functional unipolar forksheet devices with BDI are demonstrated for both N- and PMOS, for wall widths down to 10 nm. In addition, we describe a scheme to isolate adjacent source-drain structures by the forksheet dielectric wall. This scheme relies on increasing wall height, by means of active area patterning hard mask engineering, to compensate for wall losses in downstream process modules. Finally, self-alignment of gate cut to active is demonstrated morphologically.

We report on forksheet N- and PFETs co-integrated with gate-all-around nanosheet FETs. The forksheet short-channel control is on par with nanosheets down to 22nm gate length (SS SAT =66-68mV/dec). Forksheet I ON and I OFF characteristics are improved by post-channel-release wet clean optimization, attributed to gate stack interface trap density reduction. Dual work function metal gates are integrated at 17nm N-P space, highlighting a key benefit of forksheets for CMOS area scaling.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

This paper shows the importance of oxygen control at the SiGe fin surface and within the gate stack. Optimized SiN liners are required to protect SiGe fins from oxidation during a flowable CVD (FCVD) densification anneal. Suppression of oxygen diffusion or scavenging from GeO via metal electrode is essential to achieve a low-D IT SiGe gate stack. By replacing HfO 2 with other dielectrics offering lower oxygen diffusivity, impact of metal electrode deposition process as well as the HfO 2 nitridation is corroborated to be related to the oxygen diffusivity. Finally, when using an embedded B-doped Si 0.4 Ge 0.6 S/D, higher channel strain in Si 0.7 Ge 0.3 than in Si p-fins is obtained as predicted by TCAD.

This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, BPR plug barrier, and fin reveal are optimized to enable BPR scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. Ru-BPR meets BPR line R target <; 50 Ω/μm at ~2× smaller aspect ratio than W-BPR thanks to its lower resistivity and thinner TiN liner. A good VBPR pre-clean prior to TiN liner & Ru deposition with W-BPR underneath, is found to be crucial to achieve low Ru-VBPR resistance. Calibrated TCAD simulations show Ru-VBPR with thin TiN liner meets VBPR R target <; 75 Ω. W-BPR interface with Ru-VBPR shows robust electromigration for >1100 h at 5 MA/cm 2 at 330 °C.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.

This paper introduces the investigations on ultralow metal/semiconductor contact resistivity (ρc). First, we build a multiring circular transmission line model (MR-CTLM), a novel ρc test structure with simple process and high accuracy for rigorous ρc study. Based on that, we explore process options to achieve ultralow ρc on n-Si. We obtain high carrier concentration of ∼9e20 cm−3 by in situ P doped Si:P epitaxy followed by ms laser annealing. Besides, we use a pre-contact amorphization plus Ti silicidation technique to fabricate TiSix/Si:P contacts and achieve ultralow ρc of 1.5e–9 Ohm.cm2. Finally, we discuss sub-1e-9 Ohm.cm2 ρc solutions for future CMOS technology node.

Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ c ) of ∼2×10 −9 Ω·cm 2 on Si 0.3 Ge 0.7 :B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρ c on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P. A simple Ti based CMOS contact flow is thus proposed. Several B doping and activation methods on SiGe:B are also compared in this work.

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-mu m and 70-nm gate lengths. Hole mobility at 1-mu m gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

Record-low contact resistivity (pc) for n-Si, down to 1.5×10−9 Q-cm2, is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the pc for n-Si, while an additional Ge pre-amorphization implantation (PAI) before Ti silicidation further extends the pc reduction. In situ doped Si:P with P concentration of 2×1021 cm−3 is used as the substrate, and dynamic surface anneal (DSA) boosts P activation. In addition, TiOx based metal-insulator-semiconductor (MIS) contact is also studied on Si:P but is found to suffer from low thermal stability.