In this paper different methods and novel tools for failure localisation and high resolution material analysis for open TSV interconnects will be discussed. The paper shows the application of enhanced methods for the localisation of sidewall shorts in open TSV structures by adapted Photoemission Microscopy (PEM), Lock-in Thermography (LIT) and Electron Beam Absorbed Imaging (EBAC). In addition, a new highly efficient target preparation technique is presented, which allows the combination of Laser and FIB milling, in order to access TSV sidewall defects. Finally the use of this technique is demonstrated in a failure analysis case study.

In this paper different methods and novel tools for non-destructive failure localization and high resolution material analysis in 3D integrated devices will be discussed. The employed methodologies combine non-destructive fault localization with efficient and accurate target preparation to gain access for the following microstructure analysis, forming a subsequent failure analysis workflow. The concepts presented here involve the application of improved Lock-In Thermography (LIT) as well as different innovative concepts of high rate Focused Ion Beam (FIB) techniques and high resolution material characterization utilizing Electron Backscatter Diffraction (EBSD) and Transmission Electron Microscopy (TEM) with Nanospot Energy Dispersive X-ray Spectroscopy (EDS). In the first part of the paper the potential and the advantages of each of the techniques will be demonstrated with respect to their application for Through Silicon Via (TSV) technologies by means of different case studies. To illustrate the complete workflow of the approach, a failure analysis of a vertically integrated microsystem using a micro-bump technology is described in the second part.

Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for “More than Moore” solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven “open” TSV technology on the basis of a 0.35μm CMOS process.

The paper deals with demonstration of Lock-in Thermography (LIT) as a new key-method for the defect localization in modern microelectronic devices. After an introduction into the operational principle and recent advantages of LIT, three different case studies for defect localization at multi-chip, flip-chip, and stacked die devices will be presented followed by physical root cause analysis, using mechanical cross sectioning and SEM investigations.

In this paper we introduce novel tools for an improved failure analysis process flow for complex packaged microsystems. This failure analysis process flow starts with a non-destructive defect localization using an improved Lock-In Thermography (LIT). After fault isolation, a highly efficient target preparation can be performed using cross-sectioning by combined pulsed-laser ablation and high-current Focused-Ion-Beam (FIB) milling in a specifically modified FIB device. The sample quality achieved is high enough to enable improved high-resolution material analysis of cross-sectioned structures using Scanning Electron Micrography (SEM) and Electron Back-Scatter Diffraction (EBSD), particularly for the analysis of highly resistive bonding interconnects, intermetallic compound identification, and texture analysis. To illustrate the complete workflow of the approach, a failure analysis of a vertically integrated microsystem using a microinsert technology is described. The particular benefit of each step is compared to conventional approaches in failure analysis. In addition, the potential of the new failure analysis methodology for future applications using System in Package (SiP) technologies is highlighted.

This paper will present a new non-destructive approach for the 3D localization of thermally active buried defects in single chip and stacked die architectures by use of Lock-in Thermography (LIT). The basic principles concerning the thermal wave propagation through different material layers and the resulting phase shift will be presented and discussed. Based on that, the LIT application for 3D defect localization will be evaluated at both fully packaged single chip and stacked die devices by comparing theoretical and experimental data.

Microscopic Lock-In Thermography (LIT) has proven unsurpassed capability for non-destructive localization of thermally active defects like shorts or resistive opens, even through the full package. This paper briefly reviews the real-time pixel-wise lock-in methodology, as the key to the extreme temperature sensitivity. A typical LIT work-flow is demonstrated whereby the main focus of the paper is to discuss and demonstrate different ways how to activate the thermally active defects with more complex DUTs/defect signatures, requiring ATE docking.

The reduced testability of 3D integrated microelectronic systems poses severe challenges to microstructure diagnostics, fault isolation and failure analysis techniques that are required to detect and analyze electrical opens, high resistive contacts and electrical shorts of the interconnects in the wafer-bonded interface. The potential of applying advanced Scanning Acoustic Microscopy and Lock in Thermography methods for defect localization as well as the application of combined laser and Focused Ion Beam techniques for target preparation and defect diagnostics is demonstrated.

It has been shown that microscopic Lock-in-Thermography ( LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.