In last 15 years, n-type doped selective epitaxy in source and drain (S/D) for nMOS have been heavily investigated. Initial interests for nMOS S/D epitaxy were focused on carbon and phosphorus doped Si:CP film for channel strain engineering and was adapted in production. In 2012, another type of ultrahigh phosphorus doped Si:P was proposed as a replacement for Si:CP for tensile engineering. With as high as 4.5E21 doping level, such Si:P film showed comparable strain as Si:CP with 2% substitutional carbon, but with much simpler process design and quickly accepted by the industry. These ultra-high doped Si:P film also promoted interests in the mechanism for such high doping level and high strain level. In last couple years, phosphorus vacancy complexes, particularly P4V, or pseudo-cubic Si3P4, is widely accepted as the key mechanism. Although still under debate, formation of high concentration, phosphorus stabilized vacancy, up to 1E21 or 2%, is also believed to be responsible for the observed high strain. Along the same line, it was quickly discovered that ultrahigh arsenic or antimony doped films are also possible (Fig 1). And high strain Si:As is also observed with a similar strain level as Si:P, with even higher doping level, likely due to the formation of As4V complex. A group V and vacancy complex, V4V complex, is electrically neutral therefore would not contribute to carrier activation. V4V interaction with carrier would be essential to understand activation and deactivation in ultrahigh n-type doped epitaxy film. P-V interaction have been observed in early studies of bipolar device or solar device. It is also extensively studied in late 1990s to understand the USJ formation and activation. To compare with these typically implanted and annealed or diffused data, high doped Si:P and Si:As epitaxy films were deposited at different temperature and annealed with different thermal budget. Our data showed that selective Si:P as grown resistivity v.s. deposition temperature closely follow the equilibrium model based on literatures, indicating selective Si:P film as grown being near thermal equilibrium from active carrier point of view, despite one order magnitude higher P concentration (Fig.2). Selective Si:As, however, showed a different trend, with lower deposition temperature having lower resistivity. To understand the mechanism, non-selective Si:P with fast deposition rate was deposited and then annealed at deposition temperature for different time. it reveals that with fast deposition rate, initial film is activated well beyond thermal equilibrium. But it quickly deactivated within 90sec to near thermal solubility (Fig 3.). Si:As is deactivated at a much slower rate and lead to a different as grown resistivity trend. The energy favored V4V structure requires a minimum temperature to dissolve and activate the carrier. 800C is found not sufficient for Si:P and Si:As requires even higher temperature and thermal budget. To investigate the activation and deactivation, HRXRD and 4-point probe were used to study the strain and carrier concentration evolution during activation and deactivation. Unlike Si:As that always observed higher strain during deactivation from HRXRD, Si:P seems to have multiple paths for deactivation. It is found that depending on active carrier history; for example, low temperature deactivation of active carrier from random capture during epitaxy growth could involve more P4V formation therefore associated with a strain gain (Fig. 3); while for carriers gained from millisecond laser high temperature anneal, post spike annealing sometime involves strain loss during deactivation, possibly via significant interstitial P, on top formation of P4V. P4V formation during deactivation provides a model for transient diffusion enhancement in Si:P with some anneal conditions. As shown in Fig 4, only over-activated sample showed enhanced tail diffusion during 900C spike anneal, probably due to P4V silicon interstitial kick-out effect. To further investigate Si:P activation and deactivation, differential Hall effect measurement (DHEM) was used to obtain the carrier depth profile of different samples. As shown in Fig 5, 1.5E21 to 3E21 total doping level, there is minimum effect of on carrier concentration. One distinct feature on the data is the carrier degradation toward surface. It is possible during the film cool down post deposition, the surface deactivated faster, assisted from the surface flux of interstitial or vacancy. Understand the surface effect on Si:P and Si:As activation deactivation is essential to improve the contact resistance for future nodes. Figure 1

We report for the first time the implementation of SiGe buried stressors in a foundry production process at 28 nm and the observation of an additional benefit of improved short channel behavior (reduced DIBL) that results in at least 15% improvement in Idlin-Ioff independent of any benefit obtained from tensile strain. For RF applications, f(T) is projected to improve by at least 40% in n-MOSFETs with SiGe buried stressor.

Since ultra-highly doped, highly tensile strained Si:P epitaxy was reported about 10 years ago, it quickly replaced Si:CP and become key processes for advanced nodes. With greater than 3E21 doping level, these films exhibit significant tensile stress and low resistivity, both enhanced the nMOS performance. As the technology scales, contact resistance is becoming a major factor for device performance, even higher activation level is desired. In this paper, the mechanisms for high doping level and tensile strain are briefly reviewed and discussed. Despite epitaxially grown, these films showed similar thermal equilibrium behavior as implant-annealed samples and could be predicted with well established model. Diffusion and strain analysis shed some lights on the processes involved in the carrier activation and deactivation. Formation of group V - vacancy complex, V 4 V, or Si 3 P 4 -like, structure is key to understand the behavior, especially dopant diffusion and interaction with vacancy. Unlike Si:As, Si:P showed different behavior with different anneal and deposition approaches that might indicating a much more complicate deactivation path. And strong surface influence of P diffusion might present a challenge for contact engineering.

We report for the first time the implementation of SiGe buried stressors in the context of research and development of an advanced foundry FDSOI process and the observation of improved transconductance and current drive performance of n-channel FDSOI MOSFETs. Epitaxial SiGe stressors grown by CVD at Applied Materials were incorporated under the buried oxide of 300 mm FDSOI wafers by Soitec using lower temperature SOI bonding, splitting and thinning processes and the wafers were subsequently processed through an FDSOI development line at GLOBALFOUNDRIES. The use of FDSOI with buried stressor under the BOX eliminates the risk of extended defects in the epitaxial SiGe layer penetrating up into the SOI channel and also provides an opportunity to obtain a high level of strain in any semiconductor on insulator. A 70 nm thick SiGe buried stressor with 20% Ge is shown to provide a 10% improvement in I-ds(at) a fixed I-off for n-FETs with 20 nm gate length and transconductance, g(m) is correspondingly improved by 15%.

Device scaling and new applications in nanoelectronics present increasing challenges to epitaxy. Reducing thermal budgets, compatibility with novel materials, increasing topology and higher device density require new strategies for both the epitaxial film growth itself and substrate preparation. In this talk we will review specific problems for enabling low temperature epitaxial growth and discuss the impact of non-volatile contaminants beyond oxygen on Si and SiGe epitaxy. We will compare multiple potential solutions and discuss their utility and limitations.

The high peak mobility of 509 cm(2)/V . s of the chemical vapor deposition-grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The world's first GeSn p-FinFETs formed on a novel GeSn-on-insulator (GeSnOI) substrate is reported, with channel lengths L ch down to 50 nm and fin width W Fin down to 20 nm. In comparison with other reported GeSn p-FETs, record low S of 79 mV/decade, record high G m, int , of 807 μS/um (VDs of -0.5 V), and the highest G m, int /S sat , were achieved. The highest high-field hole mobility of 208 cm2/Vs (at inversion carrier density of 8×10 -2 cm -2 ) for GeSn p-FETs with CVD grown GeSn channel was also obtained.

Pseudomorphic Ge 0.91 Sn 0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge 0.91 Sn 0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on <;110> channel direction is observed using external transverse uniaxial tensile strain (~0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I on /I off ratio, and strain-enhanced mobility are obtained in this work.

In the past decade, the surge of demand for mobile devices has been tremendous, and has been a key growth engine for the semiconductor market. These novel devices have all capabilities for sophisticated mobile communication, as well as capabilities for gaming, computing, etc. To address the stringent requirements in terms of battery lifetime, device speed, and scaling, the design and manufacturing processes of mobile devices needs constant innovation. Historically, Group IV epitaxial processes such as e-SiGe source/drain have played a critical role in meeting the needs for device scaling and performance in planar devices. One dramatic change that has taken place to address device scalability is the move to the multigate architecture of the FinFET (Fin Field Effect Transistor), which enables the virtual increase of the gate length and dramatically improved electrostatic performance. Beyond FinFET, the GAA (Gate All around Transistors) device structure is one of the most promising paths for offering another disruptive leap in device scaling. This paper discusses the increasingly critical role of epitaxy applications for enabling both of these new device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices. We first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, Channel mobility, sub-fin isolation, sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Examples of these SiGe channel integration approaches include SiGe replacement channel, STI last SiGe formation, cladded SiGe and SiGe condensation. There are significant integration challenges for each of these approaches from the perspective of epitaxial growth and related processes. For example, each of SiGe channel formation schemes have some specific requirements not only on the pre-clean and/or epi growth but also on the overall CMOS integration scheme (alleviation of SiGe oxidation, recess, Fin shaping, junction formation etc.). Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored in detail for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to a new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.

Silicon Germanium (SiGe) strain relaxed buffers (SRB) are fully relaxed epitaxial layers that serve as templates for subsequent growth of tensile or compressively strained layers that can serve as N and P channels for continued scaling of Si CMOS technology. In the work reported here, we have studied thick graded SRB layers from a holistic perspective which includes SRB growth targeting defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates.

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ~7% mobility enhancement on <;110> channel direction is observed using external transverse uniaxial tensile strain of ~0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

Films of CeO2 were deposited by atomic layer deposition (ALD) using a Ce(mmp)4 [mmp = 1‐methoxy‐2‐methyl‐2‐propanolate] precursor and H2O reactant. The growth characteristics and film properties of ALD CeO2 were investigated. The ALD CeO2 process produced highly pure, stoichiometric films with polycrystalline cubic phases. Using the ALD CeO2 process, the effects of Ce doping into an HfO2 gate dielectric were systematically investigated. Regardless of Ce/(Ce + Hf) composition, all ALD CexHf1−xO2 films exhibited constant growth rates of approximately 1.3 Å/cycle, which is essentially identical to the ALD HfO2 growth rates. After high‐temperature vacuum annealing at 900°C, it was verified, based on X‐ray diffraction and high‐resolution cross‐sectional transmission electron microscopy results, that all samples with various Ce/(Ce + Hf) compositions were transformed from nanocrystalline to stabilized cubic or tetragonal HfO2 phases. In addition, the dielectric constant of the CexHf1−xO2 films significantly increased, depending on the Ce doping content. The maximum dielectric constant value was found to be nearly 39 for the Ce/(Ce + Hf) concentration of ~11%.

Semiconductor industry is in the era of transition from 2D transistors to 3D transistors (for example, FinFETs). The scaling–down of transistor source/ drain (S/D) contact area causes more challenges in reducing the S/D parasitic resistance which becomes comparable to (or even higher than) the channel resistance itself. A highly phosphorous doped Si epitaxial film on S/D is crucial to reduce the parasitic resistance in nMOSFET transistors. Besides that, 2D/3D nMOSFET transistors favor the tensile strain induced in the channel to enhance the electron channel mobility. Here we present a selective Si:P epitaxial film growth which provides both high phosphorous concentrations (>1E+21 at/cc) and high tensile strain (comparable to ~1 at.% of Csub in Si:CP). This selective Si:P epitaxial process was performed using dichlorosilane (DCS), phosphine (PH3), and hydrochloride (HCl) gases in Applied Materials Centura RP Epi system. Grown highly concentrated, highly tensile-strained Si:P (called HS Si:P) films were analyzed by techniques of high-resolution XRD (HR-XRD), four-point Rs probe, SEM, TEM, and SIMS, etc. Table 1 compares two types of Si:P epitaxial films: conventional Si:P Epi versus HS Si:P Epi. In Fig. 1(a), the total [P] by SIMS in HS Si:P epitaxial film is 1.75E+21 at/cc (~ 3 at.% in silicon), about one magnitude order higher than in conventional Si:P film, much higher than the solid solubility (~3E+20 at/cc) of phosphorous in silicon at 700°C [1]. The 0.6 mΩ-cm resistivity in HS Si:P epitaxial film indicates that only ~1.3E+20 at/cc phosphorous atoms are electrically active. In Fig. 1(b), the HR-XRD profile from HS Si:P film shows a strong tensile strain equivalent to ~0.8 at.% Csub from a Si:CP film. We assume that majority of phosphorous atoms are covalently bonded with adjacent Si atoms in a stable Si-P compound phase –pseudocubic Si3P4 which is energetically favored relative to other Si3P4 phases [2]. With the Vegard’s law (of linear relationship between lattice parameter and alloy concentration) applied between Si and pseudocubic Si3P4 (which has a smaller lattice constant than Si), the tensile strain induced in HS Si:P film matches well the HR-XRD data, as previously reported by Z. Ye et. al.[3]. Fig. 2 plots out selective HS Si:P epitaxial process sensitivity to growth temperature (675-775°C) regarding resistivity, strain, and total [P]. HS Si:P epitaxial films are stable without obvious phosphorous out-diffusion in this temperature range, which is confirmed by SIMS measurements. Both total [P] level and tensile strain decrease with the increasing temperature. Meanwhile, resistivity drops from 0.7 mΩ-cm @675°C to 0.5 mΩ-cm @725°C as more phosphorous atoms are electrically activated at higher temperature. Fig. 3 characterizes the HS Si:P film epitaxial growth on the (110) orientated substrate. The HR-XRD profile in Fig. 3(a) indicates a well-ordered HS Si:P epitaxial film grown on the (110) substrate. The TEM image in Fig. 3(b) shows a HS Si:P epitaxial film grown on (110) substrate without defects at interface, which is very significant for epitaxial growth around non-planar structures. Furthermore, Fig. 4(a) and (b) present two high-quality HS Si:P films with few defects, epitaxially grown on a planar structure and a Si fin structure, respectively. HS Si:P epitaxial films have been studied after the millisecond annealing treatment @900-1300°C in Fig. 5. After annealing, resistivity drops from 0.65 mΩ-cm @1050°Cto ~ 0.3 mΩ-cm @1150°C and above. Tensile strain in film is stable up to 1200°C. At 1250°C and above, HS Si:P epitaxial film obviously starts to partially lose the strain likely because some phosphorous atoms are released from the structure of pseudocubic Si3P4 at such high temperatures. Overall, this selective HS Si:P epitaxial process demonstrates its great potential in 2D/3D nMOSFET application.

A pseudomorphic growth of GeSn epitaxial films with [Sn] up to 16 at.% on relaxed Ge underlayer was demonstrated in a reduced pressure thermal chemical vapor deposition chamber. GeSn film resistivity can be as low as 0.3 mOhm-cm by in-situ boron doping of GeSn. Also, a GeSiSn film growth containing [Si]~24 at.% and [Sn]~4 at.% was achieved by flowing SiH4 during GeSn growth.

We systematically investigated atomic layer deposition (ALD) of HfO2, CeO2 and Ce-doped HfO2 thin films on Ge substrates by using tetrakis dimethylamino hafnium (TDMAH) and tris(isopropylcyclopentadienyl) cerium [Ce(iPrCp)(3)] precursors with H2O. The growth characteristics, chemical and electrical properties were comparatively characterized. On the basis of X-ray photoemission spectroscopy analyses, it was confirmed that the ALD CeO2 on Ge can form a stable interfacial layer composed of Ge1+ and Ge3+, leading to improved interfacial properties. In addition, Ce-doped HfO2 films with various Ce compositions (Ce:Hf = 1:1, 1:2, 1:4 and 1:8) were prepared by an ALD supercycle process on Ge substrates. Thereby, we demonstrated that overall electrical properties including dielectric constant, interface state density, hysteresis and leakage current density are significantly improved. (C) 2014 Elsevier B.V. All rights reserved.

We compared the electrical properties of HfO2, HfO2/La2O3, and La-doped HfO2 gate insulators deposited on Ge substrate using an atomic layer deposition (ALD) process. TDMAH [tetrakis(dimethylamino)hafnium] and La(iprCp)(3) [tris(isopropyl-cyclopentadienyl) lanthanum] were employed as Hf and La precursors, respectively. Chemical compositions and binding structures were analyzed by X-ray photoelectron spectroscopy (XPS). Electrical properties were evaluated by capacitance-voltage (C-V) and current-voltage (I-V) measurements. We found that incorporation of La2O3 near Ge can enhance the electrical properties of Ge MOS capacitors. The best electrical properties of 50 mV of hysteresis and mid similar to 10(12) cm(-2) eV(-1) range interface states were found for the 400 degrees C-annealed HfO2/La2O3 bilayer sample. These values are significantly better than those of ALD HfO2 gate insulators on Ge. We attribute this to the formation of LaGeOx layers on the Ge surface, which reduces Ge-O bonding. (C) 2013 Elsevier B.V. All rights reserved.

CeO(2) thin films were deposited by plasma-enhanced atomic layer deposition (PE-ALD). Novel Ce(iPrCp)(3) [tris(isopropyl-cyclopentadienyl) cerium] was used as a Ce precursor, which showed clean evaporation with no residue and good thermal stability. For PE-ALD, O(2) plasma was used as an oxidizing reactant. The PE-ALD process exhibited ALD mode with good self-saturation behavior and linear growth without any nucleation delay on Si substrate as a function of growth cycles. Additionally, it produced highly pure and nearly stoichiometric CeO(2) films with polycrystalline cubic phases. Electrical properties of Al/CeO(2)/p-Si capacitors were improved by O(2) annealing with reduction in interface state density (D(it)), hysteresis, effective oxide charge (Q(eff)) and leakage current density. These experimental results indicate that the PE-ALD CeO(2) using Ce(iPrCp)(3) precursor can be viable option as a future high-k material in the microelectronic industry. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3594766] All rights reserved.