This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH3 ashing is proposed as an alternative to O-2 ashing to improve the gate-edge profile. It was found that NH3 ashing suppresses bottom oxide growth below the thin HfO2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH3 ashing process also makes the HfO2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process. (c) 2005 The Electrochemical Society. [DOI: 10.1149/1.2131243] All rights reserved.

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility.

2006 International Conference on Solid State Devices and Materials,Effects of Optimization of Gate Edge Profile on sub-45nm Metal Gate High-k Dielectric Metal-Oxide-Semiconductor Field Effect Transistors Characteristics

The microstructural morphology and crystallization kinetics of ultrathin HfON with different thicknesses (equivalent oxide thickness, EOT) have been studied in terms of their influence on electron mobility. Cross-sectional and plan-view transmission electron microscopy showed that crystallization is significantly suppressed when HfON was less than 2 nm thick. Thinner HfON enhances electron mobility because of less transient charge trapping. Ultrathin HfON with an amorphous phase shows improved mobility, probably due to less remote coulomb scattering in addition to the absence of transient charge trapping. (c) 2006 The Electrochemical Society.

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.

This paper compares metal oxide semiconductor field effect transistor (MOSFET) characteristics of TiN metal gate deposited by atomic layer deposition (ALD) and chemical vapor deposition (CVD) on Hf-based high-k dielectrics. Despite many similarities between these two techniques, clear differences were found in device characteristics such as equivalent oxide thickness (EOT), mobility, dopant diffusion, and trap generation. ALD TiN results in a thicker EOT than CVD TiN due to its inherent purging cycle and higher process temperature, but it has a stronger resistance to dopant diffusion. The ALD TiN process also provides better interfacial characteristics, thus better device performance. (c) 2005 The Electrochemical Society.

The process module development and device characteristics of dual metal gate complementary metal-oxide-semiconductor (CMOS) with TaSiN and Ru gate electrodes on HfO2 dielectric are reported. Highly selective wet etch processes for various metal gate materials (TaSiN, TiN, and TaN) have been developed with a minimal impact on HfO2 and HfSiON. A plasma etch process is developed to etch TaSiN and Ru dual metal gate stacks simultaneously on the same wafer. Well behaved dual metal gate CMOS transistors with gate length down to 85 nm have been demonstrated. This integration method is highly versatile and can be applied to various metal gate materials. (c) 2005 The Electrochemical Society.

We report on the plasma induced damage in the TiN/HfSiO/sub 4/ gate stack, and, specifically, its impact on pMOSFETs. Plasma assisted deposition processes after the gate stack etch step appear to cause most plasma damage, manifested by greater degradation of the plate antenna structures (area intensive) compared to comb antennas (perimeter intensive). The transient charge trapping behavior of the HfSiO/sub 4/ film seems to prevent destructive dielectric breakdown. Electrical stress could generate additional traps in the film damaged by the plasma process.

Abstract Effects of composition in Hf-silicate are evaluated for CMOSFET with TiN gate. Higher k value can be achieved by reducing Si content, effective to improve EOT-Jg performance. Lower Si content is also beneficial in terms of PMOS Vt variation caused by B diffusion. However, enhanced transient charge-trapping effect (TCE) is observed from Hf-silicate with low Si content, degrading electron mobility. Hf-silicate with low Si content also shows more TCE during positive bias stress at low stress bias, which is easily de-trapped. More permanent damage is observed in the Hf-silicate with high Si content due to relatively larger amount of SiO2 portion in the film. TCE is reduced significantly when Hf-silicate scales aggressively (Tphysical ≤ 3nm), espcially for low Si content. For high performance application, scaled Hfsilicate with low Si content is desirable due to thinner EOT and less TCE.

This paper presents a novel technique for tuning the work function of metal gate electrodes. Laminated metal gate electrodes consisting of 1/spl sim/3 ultra thin (/spl sim/10 /spl Aring/) layers of Ta, TaN, Ti, TiN, Hf or HfN and bulk metal nitride gate electrodes were deposited on SiO/sub 2/, HfO/sub 2/ or HfON, followed by RTP annealing to evaluate their thermal stability. Our results show that the work function of the laminated metal gate electrodes is significantly different from their bulk electrodes counterpart. Through lamination, a TiTaN/sub x/ alloy gate is formed which exhibits NMOS compatible work function (4.35 eV) with good thermal stability up to 900/spl deg/C. Laminated metal gates consisting of 3 components exhibit pMOS compatible work function (5,0/spl sim/5.2 eV) after 1000/spl deg/C annealing and this value remains unchanged after subsequent thermal processing. Possible mechanism responsible for work function tuning using laminated gates is discussed.

Thermally stable, high-quality ultrathin (EOT=13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO/sub 2/ up to 900/spl deg/C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.