An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm/sup 2/, 0.25-/spl mu/m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.

A 5 V CMOS chip providing the D/A, A/D, filter, and a programmable gain amplifier (PGA) for HDSL and ADSL is described. The chip includes 12-bit, 10 Msample/sec converters, filters, and a PGA having 48 dB gain with 1.7 MHz bandwidth. This chip is used in an E1-rate (2.048 Mbps) ADSL transceiver achieving a bit error rate of less than 10-9 over 5.4 km of 0.4 mm twisted copper wire

Current copier circuits are used in the IC realization of a transistor-only second-order SIGMA-DELTA modulator. By using current copiers it is possible to implement the modulator without using linear capacitors as required for switched-capacitor approaches. Design considerations based on settling time and noise for a current copier circuit will be presented, along with the description of the current output D/A and the current quantizer. The modulator has been fabricated in a digital 0.9-mu-m CMOS process and achieves 13-b resolution and 12-b linearity over the voice-band frequency range.

A detailed analysis of the performance of current copier circuits is presented. These circuits allow the sampling, holding and reproduction of practically identical copies of a current without relying on the matching of circuit elements. The analysis is confirmed both by simulation results and by tests of an experimental MOS IC. Applications of these circuits include signal processors, A/D and D/A converters

An analysis of the noise characteristics of the most basic current copier cell is presented. Since MOS transistors are used, both thermal and 1/f noise sources occur. Because of sampling, the noise appearing at the output contains both sampled and continuous components. An expression is described for the power spectral density of the output current noise, allowing an assessment of the relative importance of each of the noise sources in a current copier application. A measurement of the noise spectrum of the current copier is shown.<>

A method for making practically identical copies of a sampled current without relying on the matching of circuit elements (such as capacitors or transistors) is presented. Compact circuit realizations are discussed, leading to the generation of a family of analog function blocks for the creation, copying, and manipulation of current samples, all free from dependency on element matching. Applications of these circuits include signal processors and A/D (analog-to-digital) and D/A (digital-to-analog) convertors.<>

A mixed analog/digital chip that forms the core of a medium-speed modem for use on the public switched telephone network is described. It meets CCITT and AT&T requirements for data transmission at 2400 and 1200 b/s, and the AT&T requirement for 300-b/s operation. The chip is implemented in a 1.75- mu m analog CMOS process and occupies 32.4 mm/sup 2/. The device is powered by a single +5-V supply a...

Analogue circuits are presented that can sample, hold, and make practically identical multiple copies of current signals, without the need for accurate matching of active or passive circuit components.<>

A description is given of a mixed analog/digital chip that forms the core of a low-speed modem for use over standard telephone lines. It meets CCITT and AT&T requirements for data transmission at 1200 and 2400 b/s and the AT&T requirements for 300-b/s operation. The chip is implemented in a 1.75- mu m analog CMOS process and occupies 32.4 mm/sup 2/. The device is powered by a single +or-5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given.< >