We present a reconfigurable and scalable current-based analog compute-in-memory (CIM) macro based on a split dual-port 8T (DP-8T) SRAM bitcell. This bitcell can perform MAC operations between signed 9-bit inputs and signed 9-bit weights and logical operations. Throughput is enhanced by sensing MAC and logical operations from both true and complementary bitcell sides via dual bitline sensing, without requiring external circuitry to decode the MAC output from the complementary side. To improve the signal margin and reduce the number of ADCs, we split the 8-bit magnitudes of inputs and weights into 2-bit groups and perform efficient weight encoding with a 2C-1C network combined with analog shift-and-add using 4C and 1C at each bitline. The proposed $64\times 128$ macro performs 4096 signed MAC operations in 4 cycles with a latency of 16.2 ns. The design is implemented in TSMC 65-nm technology at 1.2 V. The architecture performs linear MAC operations across different inputs, weights, and process corners. It delivers a throughput of 252.83 GOPS, an MAC energy efficiency of 10.11 TOPS/W, and a signal margin of 26 mV for signed MAC operations. In the logical compute mode, the architecture performs nor, and, nand, and or Boolean operations in a single cycle, as well as exnor and exor using additional logical gates, achieving a throughput of 3276.8 GOPS and a latency of 1.25 ns at 0.8 V. The work achieves inference accuracies of 99.1%, 91.65%, and 71.8% on MNIST, CIFAR-10, and CIFAR-100, respectively.

Static random access memories (SRAMs) are typically generated using memory compilers, where timing characterization is performed through extensive SPICE simulations. Among the key timing metrics, the read access time often determines the maximum operating frequency of SRAM macros. This work presents an analytical model for predicting the read access time of 6T SRAM arrays with reduced number of SPICE simulations for memory characterization. The model incorporates the effects of wordline rise time, load capacitance, bit-line leakage, word-line voltage, and PVT variations. The proposed models are validated using the 28 nm STMicroelectronics PDK in the ELDO SPICE environment. The results show a maximum deviation below 2% and an average error under 1%, while reducing the number of required simulations by up to 99.78%, enabling efficient SRAM timing analysis and early-stage design exploration.

As CMOS technology scales into the nanoscale regime, ensuring the reliability of digital circuits in radiation-rich environments has become a critical challenge. Standard cell libraries, which are foundational to digital design, are typically characterized using extensive SPICE simulations to capture gate delays as functions of input transition time and load capacitance. However, these libraries do not account for total ionizing dose (TID) effects, which are caused by prolonged exposure to ionizing radiation and introduce oxide-trapped charges and interface states that degrade key transistor parameters, such as threshold voltage and leakage current. This results in significant timing inaccuracies, compromising digital timing closure in mission-critical applications such as aerospace and nuclear electronics. In this work, we propose an efficient, TID-aware standard cell characterization methodology for nanoscale CMOS technologies that generates cell characterization data in standard Liberty format, enabling accurate prediction of timing closure under TID influence without incurring any SPICE simulation overhead. Our approach leverages well-calibrated 32 nm Synopsys©Sentaurus TCAD simulations and variation-aware analytical timing models to capture TID-induced degradation. These effects are incorporated into cell netlists through adjustments to the BSIM parameters to generate both pre- and post-radiation standard cell libraries. Validated using a set of reference designs, including ISCAS benchmark circuits, the proposed methodology achieves accurate path-level timing predictions under radiation while reducing SPICE simulation effort by approximately 81.25%. By bridging device-level radiation effects with cell-level timing abstraction, this scalable framework offers a practical solution for robust and radiation-resilient digital integrated circuit design in harsh environments.

We propose a novel compute-in-memory (CIM) enabled dual-port 8T (DP-8T) SRAM bitcell design, which can simultaneously perform two Boolean operations, such as NAND and OR, in a single cycle. By contrast, conventional single-port SRAM bitcells are limited to performing only one Boolean operation per cycle. We use additional logic gates to realize other Boolean operations such as XOR/XNOR and OR/AND, along with a half-adder. The proposed 64x128 design achieves a throughput of 1780.86 GOPS with an energy efficiency of 12 fJ/bit over an operating frequency range of 746.3 to 869.5 MHz. The robustness of the proposed architecture is validated by demonstrating correct functionality of all supported logic operations under worst-case process, voltage, and temperature (PVT) corners. The proposed work achieves an accuracy of 99.6% for a binarized neural network (BNN) on the MNIST dataset.

This paper presents a novel current-based analog SRAM CIM architecture for 8-bit input and 8-bit weights MAC computations. This work proposes (1) an input/weight bitsplitting approach to perform 8bx8b MAC operations in only three cycles and (2) a current-mirror circuit that enhances the signal margin by 2.6 times. A MOM-capacitive network is used for charge sharing using only 1C, 2C, and 4C capacitors instead of higher capacitor values. To compress the partial products from 8b multiplication, we introduce the “analog shift and add” operation using 1C and 8C capacitors. This methodology enhances energy efficiency and reduces ADC overhead. The proposed design features a $64 \times 128$ 6T SRAM CIM macro, which can perform 2048 8-bit MAC operations in a single clock cycle. The proposed architecture is simulated in the TSMC 65 nm technology node at 1.2 V. The architecture achieves linear MAC operations across different input and weight cases and process corners. It achieves a throughput of 146.28 GOPS and a MAC energy efficiency of 7.2 TOPS/watt while maintaining a signal margin of 44.5 mV. Additionally, our method attains an inference accuracy of 90.46% on the CIFAR10 and 72.02% on the CIFAR100 dataset, highlighting its promise as a scalable and energy-efficient solution for deep learning acceleration.

Editor's notes: The article introduces a variation-aware timing model, emphasizing aging, for the INV-Tx structure. By reducing aging-induced degradation in a thermometer encoder, this method can eliminate the need for errordetection circuits in data converters, ensuring accurate digital encoding. -Hemangee K. Kapoor, IIT Guwahati, India

This paper presents a CMOS subthreshold voltage reference (SVR) optimized for reliable operation across wide temperature and high total ionizing dose (TID) conditions, suitable for space applications. Designed in 180nm CMOS, the circuit operates fully in the subthreshold regime with radiation aware techniques including H-Gate layout transistors, guard rings, and body contacts. Simulations show stable operation from −55°C to 125°C, yielding ≈ 0.95V with a temperature coefficient of 37.7ppm/°C and power consumption of ≈ 3µW. A fabricated test chip (0.013mm2) was irradiated with Co-60 γ-rays up to 300 krad(Si), showing only 0.3% VREF degradation, negligible power variation, and no latch-up. These results confirm the proposed SVR as a compact, low-power, and radiation tolerant solution for space-grade electronics.

This work presents a novel dual-stream split wordline (DS-SWL) 6T SRAM-based 8-bit Compute-In-Memory (CIM) architecture that combines current-domain MAC computation with time-domain based weight categorization and readout for high-throughput, energy-efficient edge AI. The design performs 8-bit MAC operations in two cycles using dual bitline sensing, providing more than 4× higher throughput than bitserial schemes. The proposed architecture replaces capacitive weight categorization—which suffers from mismatch, charge loss, and area/power overhead—with a current-mirror-based voltage-to-time converter (VTC) based time domain weight categorization. The 8-bit weight is split into two 4-bit groups, with each VTC encoding the MSB and LSB of a group, reducing the total number of VTCs (as well as time-to digital converter TDCs) by half. A ${1 2 8} \times {1 3 0}$ 6T SRAM array in TSMC ${6 5} \mathrm{~ n m}$ technology at 1.2 V enables the macro to perform 4096 MACs in two cycles with 5.8 ns latency. The CIM achieves 706.2 GOPS throughput, 33.23 TOPS/W energy efficiency, and a 30 mV signal margin, delivering inference accuracies of 99%, 92.15%, and 72.4% on MNIST, CIFAR-10, and CIFAR-100, respectively.

In view of the advantages of the single phase adiabatic circuitry, an extensive circuit analysis is carried out for the single phase adiabatic designs and conventional CMOS design at 90 nm CMOS technology node. The single phase power clock operation is employed to the efficient MOSFET diode based quasi static adiabatic logic. In order to validate the results, the CAL and SCAL-D circuits are simulated and then their application the Ripple Carry Adder (RCA) design is thoroughly analyzed for energy loss, area, technology scaling and supply voltage scaling. The single phase adiabatic RCA circuit is driven by an energy-efficient PCG. This work gives the 2 to threefold energy saving over conventional CMOS circuit. The single phase adiabatic circuit proves its candidature for ultra low power digital circuit design.

This work presents an energy-efficient multi-bit (8-b) current-based analog SRAM compute-in-memory (CIM) architecture for MAC operations. Our key idea is to group 8-bit inputs and weights into 2-bit segments for performing MAC operations. This improves signal margin without requiring external circuitry. We leverage a 1C-2C capacitive network for efficient weight encoding and also use an analog shift-and add technique for accumulating partial sums with only 1C and-4C capacitors, thus avoiding the need for higher capacitor values. This approach enhances charge redistribution efficiency and minimizes ADC overhead. The proposed design features a 64x128 6T SRAM array, which can perform 2048 8-bit MAC operations in four cycles with a latency of 15ns. The architecture is implemented in TSMC 65nm technology at 1.2V. The architecture maintains linear MAC operations across different input and weight cases and process corners. The proposed CIM macro delivers a throughput of 136.5 GOPS and MAC energy efficiency of 6.18 TOPS/W while maintaining a signal margin of 32 mV. Our approach achieves an inference accuracy of 98.62%, 90.38% and 69.46% on MNIST, CIFAR-10 and CIFAR-100, respectively.

This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (V-th) denoted by AV(th) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of AVth is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28 nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately similar to 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.

The semiconductor industry is increasingly adopting multi-die technologies, such as 2.5D and 3D IC structures, which utilize both lateral and vertical interconnects. These inter-die interconnects behave similarly to traditional intra-die interconnects; however, they are generally larger, which causes their parasitic resistance and inductance to become significant factors. This, in turn, impacts its input effective capacitance (C-eff), leading to delays and waveform distortion in the signals that propagate through them. In this work, we present a simple, intuitive, and widely applicable closed-form analytical model for estimating C-eff and the resulting waveforms at both the driving and receiving ends of long inter-die interconnects, considering all of its RLC components. The C-eff is modelled piecewise, with well-defined boundaries based on the characteristics of the driver and interconnect. In future, this piecewise C-eff approach could be integrated into static timing analysis (STA) engines for timing analysis and could support optimized buffer design methodologies for multi-die systems that include long inter-die interconnects. We evaluate our approach using a pi-model of the interconnect and the validated using TSMC 64nm PDK. The proposed method demonstrates strong agreement with SPICE results regarding waveform matching, with a maximum error of 4% in a few scenarios.

In this paper, we present a detailed comparative performance analysis between MoS2 and WS2 2-D MOSFETs under varying temperature conditions. Although the WS2 device shows 68.55 mu A/mu m better on current at room temperature than the MOS2 one, the off-state leakage current is found to deteriorate in both cases with an increase in temperature mainly due to thermionic emission. Moreover, a lowering of R-ch and better transconductance behaviour at higher temperatures is observed which is related to the predominant self-heating effect in these nanoscale SB devices. Lastly, it is seen that a thin gate oxide with a mediocre dielectric constant provides the best short-channel performance and device electrostatics for the two devices under consideration.

The floating body (FB) effect in Partially Depleted (PD) Silicon-on-Insulator (SOI) devices has the potential to be utilized for enhancing energy efficiency. This is because the floating body potential can be leveraged to modulate the threshold voltage, thereby improving headroom in analog circuit design and thus enabling low-voltage operation. We propose a novel physics-based FB potential model that considers impact ionization (II) and selfheating (SH) effects for low terminal bias (VDS and VGS) operation. Subsequently, the proposed FB potential model is utilized to develop a model for the small-signal parameters (gm and Ro) of a PD SOI device. This proposed model will be useful for an analog designers to design an energy-efficient analog circuits by considering hitherto unused FB effects in mature PDSOI technology.

In multi-bit analog compute in-memory (CIM) architecture, inadequate signal margin (SM) between two consecutive multiplication and accumulate voltages is a major problem for robust MAC operation. A robust fully differential multi-bit analog multiplication and accumulate (FDMAC) scheme using dummy rows to enhance the signal margin is proposed in this paper. The proposed scheme achieves 1.42x, 2.86x, 7.27x, and 12.8x higher SM than state-of-the-art. The proposed scheme achieves robust MAC operation with variability (s/mu) of 3%, which is 2.87x and 3.23x lower than reported works. The energy-efficiency of proposed architecture is 2.5 TOPS/W at 1 V supply voltage in 65 nm CMOS technology. The inference accuracy of the architecture is 98.6 % and 84.73% for MNIST and CIFAR-10 dataset respectively for LeNet-5 CNN model. The Figure of Merit (FoM) of proposed architecture is 33.33, which is 2.7x, 4.9x, 5.3x, 12x, and 26.2x higher than the reported works.

A multiscale model that determines self-heating effect (SHE)-induced and mechanical deformation-accelerated trap generation and also assesses its impact on dielectric breakdown (BD) in hafnium-oxide (HfO2)/(interfacial)silicon dioxide (SiO2)-based gate-stack in a 5-nm stacked nanosheet field effect transistor (SNFET) has been developed here. Initially, T-CAD thermodynamic (TD) simulation was performed to estimate nonuniform SHE across SNFET under applied SHE bias, which was later supplemented by a multiphysics-based simulation as was executed to extract process (anneal) derived residual stresses from both silicon nanosheets and surrounded dielectric layers. Furthermore, simulated deformation profiles were provided as inputs to an ab initio simulation module, which calculated the spatial variations of defect neutral oxygen vacancies (NOVs) formation energies (FEs) either across HfO2 or (interfacial) SiO2 molecules. Updated FEs and local temperatures of dielectrics due to SHE in SNFET were then fed as inputs to a standard thermochemical trap generation model for profiling trap generation rates within the dielectric layers. Later, the critical path (CP) of dielectric BD was assessed by a shortest path search algorithm, which estimated the costs of all probable percolating paths through joining the trap generation sites between gate and nanosheet channels and then organized them as per their precedence for analyzing the critical BD path.

This work presents a robust multi-bit compute-in-memory architecture using a 4T1C eDRAM cell. The proposed 4T1C eDRAM has a decoupled read and write port. Hence, avoid the destructive read operation to support multiple row activation during the MAC operation and enhance the system's throughput. The throughput of the proposed architecture is 4.09 TOPS, which is 20x higher than the state-of-the-art. The `345' relative PVT variation of the proposed architecture is 2%, 4.26x lower than the state-of-the-art. The energy efficiency of the proposed architecture is 8.71 TOPS/W at 0.8 V supply voltage. The achieved inference acuracy is 97.4% for MNIST data set. The FoM of the proposed architecture is 17.81, which is 172x higher than the state-of-the-art.

In this paper, we present an area and energy efficient multi-bit signed SRAM based time-domain compute-in-memory (TDCIM) architecture. We have proposed an area efficient time-domain multiplication bit-cell (TDMC) for signed/unsigned operation. The proposed TDMC is 1.5x times area efficient than state-of-the-art. The work uses a time domain computing approach that uses combination of delay and pulse width to represent the equivalent multiplication and accumulation (MAC) operation performed. The proposed TDCIM focuses on improving the energy efficiency of the MAC operation. A time to digital converter (TDC) is used instead of analog to digital converter (ADC) to save power and area consumption. It achieves 1.3x higher energy efficiency compared to state of the art. The designed architecture has been implemented using a 28 nm FDSOI STM technology, resulting in the development of an 8 Kb TDCIM macro. This work achieves a normalized energy efficiency of 1910.45 TOPS/W at VDD of 0.8 V. The architecture achieves an inference accuracy of 91.20% on the CIFAR-10 dataset with 8-bit precision in inputs and weights.

Deploying Sparse Ternary Neural Networks on edge devices is in the areas of computational efficiency and energy optimization is a challenging task. This work presents a new FPGA-based accelerator integrating reinforcement learning and neural architecture search to dynamically optimize Sparse Ternary Neural Networks (Sparse TNN) for real-time applications. The design adopts adaptive pruning and quantization techniques for computational complexity and power consumption with the desired accuracy. Experimental evaluation on the Xilinx ZCU102 platform achieves up to 16.46 x speedup compared to dense models at less than 1% accuracy loss and achieves state-of-the-art performance on benchmarks such as Google Net and MobileNetV2. This work holds promise for resource-constrained high-throughput applications, bringing FPGA-based deep learning closer to efficiency and scalability.

As semiconductor technology advances to sub10 nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7 nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7 nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N -stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.